ishan.dalal
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1) How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM's performance?
2) What's the critical path in a SRAM?
3) In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?
4) For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)
Thanks in advance :smile:
2) What's the critical path in a SRAM?
3) In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?
4) For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)
Thanks in advance :smile: