Quartus - range in generation scheme must be static

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shaiko

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Hello,

I got the following error while compiling my project:
Error (10806): VHDL error at controller_write_fifo.vhd(128): range in generation scheme must be static
Click to expand...
this is what written in line 128 of the mentioned file:
Code: 
write_pointer_to_write_address : for index in OUT_TYPE_ARRAY_UNSIGNED_ADDRESS_1 ' range
generate 
OUT_TYPE_ARRAY_UNSIGNED_ADDRESS_2 ( index ) <= 
OUT_TYPE_ARRAY_UNSIGNED_ADDRESS_1 ( index ) ( OUT_TYPE_ARRAY_UNSIGNED_ADDRESS_1 ( 0 ) ' high - 1 downto 0 ) ;
end generate write_pointer_to_write_address ;
"OUT_TYPE_ARRAY_UNSIGNED_ADDRESS_1" is an entity output port defined as follows:
Code: 
OUT_TYPE_ARRAY_UNSIGNED_ADDRESS_1 : buffer type_array_unsigned ( 0 to POSITIVE_CONFIGURATION_2 - 1 ) ( positive ( log2 ( real ( POSITIVE_CONFIGURATION_2 ) ) ) downto 0 ) ;
POSITIVE_CONFIGURATION_2 is a generic.
Why does Quartus consider the range of OUT_TYPE_ARRAY_UNSIGNED_ADDRESS_1 to be non static?
 

because its not globally static, its only locally static.

What is POSITIVE_CONFIGURATION_2?
 

This is how I defined the POSITIVE_CONFIGURATION_2 generic:
Code: 
POSITIVE_CONFIGURATION_2 : positive := 4;
Modelsim chews up this code - so why won't Quartus?
Any VHDL rules broken?

Note:
Everything works flawlessly when I rewrite
Code: 
write_pointer_to_write_address : for index in [COLOR="#FF0000"]OUT_TYPE_ARRAY_UNSIGNED_ADDRESS_1 ' range[/COLOR]
generate 
OUT_TYPE_ARRAY_UNSIGNED_ADDRESS_2 ( index ) <= 
OUT_TYPE_ARRAY_UNSIGNED_ADDRESS_1 ( index ) ( OUT_TYPE_ARRAY_UNSIGNED_ADDRESS_1 ( 0 ) ' high - 1 downto 0 ) ;
end generate write_pointer_to_write_address ;
to
Code: 
write_pointer_to_write_address : for index in [COLOR="#FF0000"]0 to POSITIVE_CONFIGURATION_2 - 1[/COLOR] 
generate 
OUT_TYPE_ARRAY_UNSIGNED_ADDRESS_2 ( index ) <= 
OUT_TYPE_ARRAY_UNSIGNED_ADDRESS_1 ( index ) ( OUT_TYPE_ARRAY_UNSIGNED_ADDRESS_1 ( 0 ) ' high - 1 downto 0 ) ;
end generate write_pointer_to_write_address ;
 

TrickyDicky,

Would you agree that my code should work with Quartus ?
 

I wouldnt agree on how anything with a 2008 flavour should work or not in quartus. It doesnt have full 2008 support. Until altera and xilinx have full support for 2008, I wont be using anything other than '93 for synthesis.

I would raise a support ticket though, as it does appear to be falling foul of their listed support for 2008.
 
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    shaiko

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Why are you using port type "buffer"?
I have made a decision to never use "buffer" ports. If I remember correctly, you get in trouble if you want to instantiate a block using "buffer" ports inside a block that uses normal "out" ports. So, "buffer" ports are like a disease that spreads to the containing blocks.
 

Why are you using port type "buffer"?
Click to expand...

In general, I stopped using buffers myself.
In this particular case, I used "out" at first...

Even though Quartus claims to support VHDL 2008 - it doesn't...So compilation fails when you read back an "out" port.
I used "buffer" as a quick fix to avoid rewriting my code with intermediate signals.
 

shaiko said:
Even though Quartus claims to support VHDL 2008 - it doesn't...So compilation fails when you read back an "out" port.
I used "buffer" as a quick fix to avoid rewriting my code with intermediate signals.
Click to expand...
I think you are OK until you try to connect a "buffer" port to an "out" port.
 

shaiko said:
Even though Quartus claims to support VHDL 2008 - it doesn't...So compilation fails when you read back an "out" port.
Click to expand...

did you change Quartus vhdl synthesis setting to VHDL-2008 ?
 

Stupid question from a VHDL noob. What's the difference between a buffer and an out port in vhdl, and mostly what is the horrific contagion part of it?

I was thinking maybe registered vs unregister outputs of modules, but I couldn't really see how that would be a bad thing other than using up FFs.

And taking my own advice of "google it you lazy person" I found this one:
https://vhdlguru.blogspot.com/2011/02/how-to-stop-using-buffer-ports-in-vhdl.html

That difference in handling of internal module vs fpga output would seem to suggest something along the lines of automatic instantiation of OBUFs. Because if it's that I can sortof see it. You only want those on your output pins, and not in modules somewhere in the fabric. And obviously there are no OBUFs in the fabric so maybe then the synthesizer does something novel. A bit along the lines of "no tristates inside the fabric". Something like that??

Excuse the noob question, I am trying to improve my read-only VHDL skills...

PS: "good" to see that the VHDL part of the world suffers just as bad as the verilog part. What? Support modern language constructs in our synthesizer? NEVER! Wake me up when it is 2020, maybe then we have full system verilog support in vendor specific synthesizers.
 
Last edited:

mrflibble said:
Stupid question from a VHDL noob. What's the difference between a buffer and an out port in vhdl, and mostly what is the horrific contagion part of it?
Click to expand...

An 'out' cannot be 'read' which means that it cannot be used on the right hand side of an assignment or used in a comparison, etc. A buffer can be used in those situations.

Examples:
my_out: out ...
my_buffer: buffer ...

xxx <= my_out and zzz; -- Illegal since my_out is an output only
xxx <= mu_buffer and zzz; -- Legal

if (my_out = '1') then --- Illegal since my_out is an output only
if (my_buffer = '1') then --- Legal

The contagion part is mostly overreaction but still a concern depending on which synthesis tool that you commonly use. The problem was that synthesis tools wouldn't always handle 'buffer' properly although I don't recall any more detailed specifics of how they would mess up. The usual work around is to define an internal signal and use that everywhere and then have that internal signal then get assigned to the output.

Kevin Jennings
 

They never claimed full support - they only claim support for certain features.
ie. Use at your own peril.

PS. VHDL 2008 allows you to read out ports, so buffer is pretty redundant.
 
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    shaiko

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shaiko said:
Why does Quartus consider the range of OUT_TYPE_ARRAY_UNSIGNED_ADDRESS_1 to be non static?
Click to expand...
Since OUT_TYPE_ARRAY_UNSIGNED_ADDRESS_1 is a two dimensional array, can you try OUT_TYPE_ARRAY_UNSIGNED_ADDRESS_1 ' range(1) in place of OUT_TYPE_ARRAY_UNSIGNED_ADDRESS_1 ' range?

Also, it might be useful if you would post some form of complete but stripped down code that demonstrates the problem so we wouldn't have to guess and recreate files that you're using.

Kevin Jennings
 

mrflibble said:
Stupid question from a VHDL noob. What's the difference between a buffer and an out port in vhdl, and mostly what is the horrific contagion part of it?
Click to expand...
I have got fragments of information about this, and I have puzzled together my interpretation, which can be wrong. It works for VHDL-93 and earlier:

1. You can't read an "out" port in VHDL because you can't be sure of the value. Somebody may connect the port to another driver, so the resulting value can be resolved to something different from what you are driving.

2. You can access the driving value by using an intermediate signal or the DRIVING_VALUE attribute.

3. "buffer" is an "out" port which is illegal to connect to other drivers. This means that the value is always the same as you are driving. Because of this, it is legal to read it inside the driving process.

4. Because it is illegal to connect a "buffer" output to other drivers, this property must propagate to the outer layers. This means that when you instantiate a block with "buffer" outputs, you can't connect them to normal "out" outputs. This is a pain in the a** and the reason for me to avoid "buffer" completely.

As I said, something can be wrong here. I have ignored "buffer" completely since my decision to avoid them.
 

Ahah, I can see how that would work. Thank you for the explanation.
 

axcdd,
did you change Quartus vhdl synthesis setting to VHDL-2008 ?
Click to expand...
Yes.

K-J
Since OUT_TYPE_ARRAY_UNSIGNED_ADDRESS_1 is a two dimensional array, can you try OUT_TYPE_ARRAY_UNSIGNED_ADDRESS_1 ' range(1) in place of OUT_TYPE_ARRAY_UNSIGNED_ADDRESS_1 ' range?
Click to expand...
How will that help ?
I'm interested in the range of the depth - NOT the range of the width...
 

shaiko said:
How will that help ?
I'm interested in the range of the depth - NOT the range of the width...
Click to expand...
Actually it won't help. I misread the definition. You don't have a 2d array, you have an array of an array.
 

Actually it won't help. I misread the definition. You don't have a 2d array, you have an array of an array.
Click to expand...

Why not?
"OUT_TYPE_ARRAY_UNSIGNED_ADDRESS_1" is an array of std logic vectors...
 

shaiko said:
Why not?
"OUT_TYPE_ARRAY_UNSIGNED_ADDRESS_1" is an array of std logic vectors...
Click to expand...

Yes - it is a 1D array of 1D arrays. Range(1) is for 2+D arrays.

Your problem is a quartus bug. You need to raise a support request.
 
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