BartlebyScrivener
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I have a project written in SystemVerilog. Once upon a time I got it to synthesize in Quartus. Now when I try I am getting errors where there shouldn't be. For instance, in many of the modules I use the line
As the first line, but quartus wants me to put a ";" after it, which isn't how it's supposed to be. Even if I put a ";" after it, quartus still isn't happy. Then it asks for a description!
What's going on?
Thanks.
Code:
`include "ENoC_Config.sv"As the first line, but quartus wants me to put a ";" after it, which isn't how it's supposed to be. Even if I put a ";" after it, quartus still isn't happy. Then it asks for a description!
What's going on?
Thanks.