[SOLVED] Quartus : Including files

kvn0smnsn · Nov 22, 2022

I've asked questions in this forum about writing Verilog code used in EDA Playground, and had good look getting answers. Is this forum also for questions we have about Quartus? I have succeeded in getting Quartus to download to a FPGA an implementation of a single Verilog file, sometimes with multiple modules in that one Verilog file. Now I've separated the modules so that each one is in its own file, and I'm having trouble figuring out how to use Quartus to compile them.

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Changed original title to something now minimally related to the question.

FvM · Nov 22, 2022

Thread moved to more appropriate FPGA forum.

Just add all verilog files to the project, select the top design file, press start compilation.

kvn0smnsn · Nov 22, 2022

FvM said:
Thread moved to more appropriate FPGA forum.

Just add all verilog files to the project, select the top design file, press start compilation.

Okay, I moved files "FullAdder.v":

Code:

module FullAdder( cOut, sum, aOp, bOp, cIn);
  output cOut;
  output sum;
  input  aOp;
  input  bOp;
  input  cIn;

  assign cOut = aOp & bOp | aOp & cIn | bOp & cIn;
  assign sum  = aOp ^ bOp ^ cIn;
endmodule

, "AddVector.v":

Code:

`include "FullAdder.v"

module AddVector #( nmBits = 1)
                 ( sum, aOp, bOp);
  output [ nmBits  :0] sum;
  input  [ nmBits-1:0] aOp;
  input  [ nmBits-1:0] bOp;
  wire   [ nmBits  :0] carry;

  assign carry[ 0]    = 1'b0;
  assign sum[ nmBits] = carry[ nmBits];

  genvar bt;
  generate
    for (bt = 0; bt < nmBits; bt = bt + 1)
    begin
      FullAdder fa( carry[ bt + 1], sum[ bt], aOp[ bt], bOp[ bt], carry[ bt]);
    end
  endgenerate

endmodule

, "Mux.v":

Code:

module Mux #( nmBits = 1)
           ( result, control, hgVal, lwVal);
  output [ nmBits-1:0] result;
  input                control;
  input  [ nmBits-1:0] hgVal;
  input  [ nmBits-1:0] lwVal;

  genvar bt;
  generate
    for (bt = 0; bt < nmBits; bt = bt + 1)
    begin
      assign result[ bt] = control ? hgVal[ bt] : lwVal[ bt];
    end
  endgenerate

endmodule

, "DvByTn.v":

Code:

`include "AddVector.v"
`include "Mux.v"

module DvByTn( quotient, remainder, dividend);
  output [ 2:0] quotient;
  output [ 3:0] remainder;
  input  [ 5:0] dividend;
  wire   [ 6:0] sum40;
  wire   [ 6:0] sum20;
  wire   [ 5:0] sum10;
  wire   [ 5:0] result40;
  wire   [ 4:0] result20;
  wire   [ 3:0] result10;

  AddVector #(6) av40( sum40, dividend, 6'b011000);   // Subtract 40.
  AddVector #(6) av20( sum20, result40, 6'b101100);   // Subtract 20.
  AddVector #(5) av10( sum10, result20, 5'b10110 );   // Subtract 10.

  // For each mux, pass through the least significant bits of the sum if the
  // most significant bit is high, which indicates the subtraction is positive;
  // otherwise pass through the value before the subtraction.
  Mux #(6) mx40( result40, sum40[ 6], sum40[ 5:0], dividend);
  Mux #(5) mx20( result20, sum20[ 6], sum20[ 4:0], result40[ 4:0]);
  Mux #(4) mx10( result10, sum10[ 5], sum10[ 3:0], result20[ 3:0]);

  assign quotient[ 2] = sum40[ 6];
  assign quotient[ 1] = sum20[ 6];
  assign quotient[ 0] = sum10[ 5];
  assign remainder    = result10;

endmodule

, "DispDigit.v":

Code:

// Convert a hexadecimal number into its 7 segment representation for display.
module DispDigit( nSegs, hx_nmbr);
  output [7:0] nSegs;
  input  [3:0] hx_nmbr;
  wire         w_a;
  wire         w_b;
  wire         w_c;
  wire         w_d;
  wire         w_ap;
  wire         w_bp;
  wire         w_cp;
  wire         w_dp;
  wire         w_abcpd;
  wire         w_abdp;
  wire         w_apbcpdp;

  assign w_a       = hx_nmbr[ 3];
  assign w_b       = hx_nmbr[ 2];
  assign w_c       = hx_nmbr[ 1];
  assign w_d       = hx_nmbr[ 0];
  assign w_ap      = ~ w_a;
  assign w_bp      = ~ w_b;
  assign w_cp      = ~ w_c;
  assign w_dp      = ~ w_d;

  assign w_abcpd   = ~ (w_a  & w_b & w_cp & w_d);
  assign w_abdp    = ~ (w_a  & w_b & w_dp);
  assign w_apbcpdp = ~ (w_ap & w_b & w_cp & w_dp);

  assign nSegs[ 0]
       = ~ (w_apbcpdp & ~ (w_ap & w_bp & w_cp & w_d) & w_abcpd
                      & ~ (w_a & w_bp & w_c & w_d));
  assign nSegs[ 1]
       = ~ (~ (w_b & w_c & w_dp) & ~ (w_a & w_c & w_d) & w_abdp
                                 & ~ (w_ap & w_b & w_cp & w_d));
  assign nSegs[ 2]
       = ~ (~ (w_a & w_b & w_c) & w_abdp & ~ (w_ap & w_bp & w_c & w_dp));
  assign nSegs[ 3]
       = ~ (~ (w_bp & w_cp & w_d) & ~ (w_b & w_c & w_d)
                                  & ~ (w_a & w_bp & w_c & w_dp) & w_apbcpdp);
  assign nSegs[ 4]
       = ~ (~ (w_ap & w_d) & ~ (w_ap & w_b & w_cp)
                           & ~ (w_a & w_bp & w_cp & w_d));
  assign nSegs[ 5]
       = ~ (~ (w_ap & w_bp & w_c) & ~ (w_ap & w_bp & w_d) & ~ (w_ap & w_c & w_d)
                                  & w_abcpd);
  assign nSegs[ 6]
       = ~ (~ (w_ap & w_bp & w_cp) & ~ (w_a & w_b & w_cp & w_dp)
                                   & ~ (w_ap & w_b & w_c & w_d));
  assign nSegs[ 7] = 1'b1;

endmodule

, and "Join.v":

Code:

`include "DvByTn.v"
`include "DispDigit.v"

module Join( msDig, lsDig, nmbr);
  output [ 7:0] msDig;
  output [ 7:0] lsDig;
  input  [ 5:0] nmbr;
  wire   [ 3:0] qtnt;
  wire   [ 4:0] rmndr;

  DvByTn dbt( qtnt, rmndr, nmbr);
  DispDigit ddM( msDig, qtnt);
  DispDigit ddL( lsDig, rmndr);

endmodule

into directory "ECE3740_FPGA_Projects\Dbt_2"; added them all to the project; opened "Join.v"; and clicked <Processing->Start Compilation>. I got a whole bunch of error messages, beginning with:

Code:

10644 Verilog HDL error at Mux.v(10): this block requires a name
10112 Ignored design unit "Mux" at Mux.v(1) due to previous errors
...
10644 Verilog HDL error at Addvector.v(15): this block requires a name
10112 Ignored design unit "Addvector" at AddVector.v(3) due to previous errors
10644 Verilog HDL error at Mux.v(10): this block requires a name
10112 Ignored design unit "Mux" at Mux.v(1) due to previous errors
10112 Ignored design unit "DvByTn" at DvByTn.v(4) due to previous errors
10112 Ignored design unit "DispDigit" at DispDigit.v(2) due to previous errors
10112 Ignored design unit "Join" at Join.v(4) due to previous errors
...
10228 Verilog HDL error at FullAdder.v(1): module "FullAdder" cannot be declared more than once

This confused me, because EDA Playground didn't give me any complaints like this at all. What does it mean about the mentioned blocks requiring a name? How do I give them names? And why is it saying that (FullAdder) cannot be declared more than once? It looks to me like I'm only declaring it once.

FvM · Nov 22, 2022

Apparently Quartus Verilog compiler is expecting a block name for the generate block. May be a matter of the selected default language version. Just follow the block name syntax in your Verilog text book or tutorial.

Code:

  generate
    for (bt = 0; bt < nmBits; bt = bt + 1)
    begin :a
      assign result[ bt] = control ? hgVal[ bt] : lwVal[ bt];
    end
  endgenerate

Regarding declaring modules more than once, you should stop the `include nonsense. Review the respective suggestions in your previous thread.

https://www.edaboard.com/threads/getting-no-such-file-or-directory-m-but-files-are-there.404912/post-1744968

ads-ee · Nov 23, 2022

Don't use includes for adding modules into other code. That isn't the intent for the include directive. The only time I've ever seen this done was to create a single Verilog file that had all the files in the project referenced with includes to make it easier to compile the entire design, e.g. vlog -work work top_inc.v.

I recall there were weird quirky things that would result from doing this, but I don't remember the details.

I recommend that you just create a Modelsim do file that has all the vlog/vcom statements to compile the entire design. This also won't suffer from having to put in even more includes to check if something was already compiled before.

It almost seems like this Verilog question is caused by learning VHDL and applying how VHDL requires that you declare components and have them compiled in the library before you use them in another VHDL file to Verilog. FYI Verilog doesn't require you to compile a module before it's used in another module like VHDL does.

As an example Modelsim doesn't report missing Verilog modules until you run vsim and then it will complain about missing modules or incorrect port connections as it loads the design. For VHDL Modelsim will report issues with the instantiated components when compiling the file with vcom, which is why I've seen a lot of people use some sort of components_pkg.vhd file that has all the component declarations of their design included as a library in every file.

kvn0smnsn · Nov 24, 2022

Thanks, everybody; your comments helped me figure out how to name my blocks, and now everything is working.

[SOLVED] Quartus : Including files

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