LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY test_hdl IS
port(
test_out : out signed (7 downto 0);
clk : IN std_logic
);
END ENTITY test_hdl;
ARCHITECTURE test1 OF test_hdl IS
BEGIN
p0:process(clk)
variable vec: signed (15 downto 0):= "1000000010000011";
variable sum : signed (7 downto 0):= (others =>'0');
begin
if (rising_edge(clk)) then
sum := vec(15 downto 8) + vec(7 downto 7);
test_out <= sum;
end if;
end process;
END ARCHITECTURE test1;