[SOLVED] Quartus II synthesis error

[rakeshk.r]

I am using Quartus II 11.1 version for synthesis. I have included ieee.std_logic_1164.all and ieee.numeric_std.all packages in my vhdl file. I am trying to synthesize a vhdl file which works fine in simulation. I don't understand the reason behind this synthesis error. Could someone help me out with their ideas to solve this error. Thank you. The concerned vhdl line and error report is shown below.

variable mul_reg1 : signed ((2*(data_width))-1 downto 0);
variable rnd_reg1 : signed (data_width -1 downto 0);
line161: rnd_reg1 := mul_reg1((2*data_width)-1 downto data_width)+ mul_reg1(data_width-1); -- where data_width : positive := 18 , declared in Generic.

Performing Synthesis ...
Info: Running Quartus II 32-bit Analysis & Synthesis
.....
Error (10327): VHDL error at comp_x_gen.vhd(161): can't determine definition of operator ""+"" -- found 0 possible definitions
Error: Quartus II 32-bit Analysis & Synthesis was unsuccessful. 1 error, 0 warnings
Error: Peak virtual memory: 330 megabytes
Error: Processing ended: Wed Dec 11 10:53:54 2013
Error: Elapsed time: 00:00:03
Error: Total CPU time (on all processors): 00:00:02
QIS Synthesis completed successfully

 

[TrickyDicky]

Please show the full code, not just a small snippet.

 

[SynthWorks]

On line 161, you are adding signed + std_logic. While this is supported by VHDL-2008 version of numeric_std, it is not supported by previous versions.

Instead of using indexing, use a slice to form your second argument, this way you are adding signed + signed which is supported:

rnd_reg1 := mul_reg1((2*data_width)-1 downto data_width)+ mul_reg1(data_width-1 downto data_width-1);

The slice, mul_reg1(data_width-1 downto data_width-1), gives you a one element array of type signed, rather than the indexing mul_reg1(data_width-1) which gives you std_logic.

 

[rakeshk.r]

I actually did the below to solve the problem. Like SynthWoks said the reason is, i was doing addition of a vector with a single bit, which was not supported.
variable tmp_reg1 : signed(data_width-1 downto 0):=(others=>'0');
tmp_reg1(0) := mul_reg1(data_width-1);
rnd_reg1 := mul_reg1((2*data_width)-1 downto data_width)+ tmp_reg1;
But i am not sure as Synthworks says mul_reg1(data_width-1 downto data_width-1) would work ? I will have to test it and see.

 

[TrickyDicky]

It should work fine - that 1 bit slice gives a signed array of length 1, so should add correctly. But a signed array of length one can only represent -1 or 0. are you sure thats what you really want? The + function will sign extend the shorter of the two inputs to the length of the longer one.

So the new code you posted is not the same as your origional code.

- - - Updated - - -

An easier way to do rounding is +1 and chop off the LSBs.

 

[rakeshk.r]

@TrickyDicky yes,I don't want that to happen. Let us consider an small example depicting the scenario above. I did what SynthWorks said. But the result 'sum' is "0111 1111" which is wrong rather it should have been "1000 0001". so i don't think mul_reg1(data_width-1 downto data_width-1) will only represent mul_reg(data_width-1) bit. Isn't it ?

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

ENTITY test_hdl IS
  port(
       test_out : out    signed (7 downto 0);
       clk      : IN     std_logic
     );
END ENTITY test_hdl;
ARCHITECTURE test1 OF test_hdl IS
BEGIN

p0:process(clk)
variable vec: signed (15 downto 0):= "1000000010000011";
variable sum : signed (7 downto 0):= (others =>'0');
begin
  if (rising_edge(clk)) then 
       sum := vec(15 downto 8) + vec(7 downto 7);
       test_out <= sum;
  end if;
end process;
END ARCHITECTURE test1;

 

[SynthWorks]

variable tmp_reg1 : signed(data_width-1 downto 0):=(others=>'0');
tmp_reg1(0) := mul_reg1(data_width-1);
rnd_reg1 := mul_reg1((2*data_width)-1 downto data_width)+ tmp_reg1;

What you did looks correct for what you are doing. What I did is different. As TrickyDicky said, the one bit signed value will only hold the values 0 and -1, and hence, the result will not work for what you are doing.

An easier way to do rounding is +1 and chop off the LSBs.

Provided you do it on the slice, mul_reg1((2*data_width)-1 downto data_width -1) you would be similar to what rakeshk.r did.