Quartus Error: Object is used but not declared

Status
Not open for further replies.

Xevon

Newbie level 1
Joined
Nov 29, 2012
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Visit site
Activity points
1,308
I am getting : Error (10482): VHDL error at sevensegproj.vhd(144) : object 'e' is used but not declared.

As far as I can tell it is declared.. just started using vhdl this semester for my class. I am making a seven segment display and am in the middle of debugging so excuse my lack of knowledge. Here is a portion of the code where I think the error may be (the code is like 500 lines long probably shouldn't post it all so only doing a portion) :

entity Proj is
port
(
A: in std_logic_vector (2 downto 0);
A1: in std_logic;
A2: in std_logic_vector (3 downto 0);
A3: in std_logic;
A4: in std_logic;
LS, RS: out std_logic_vector (6 downto 0)
);
END Proj;

Architecture struct of Proj is
--skipping a lot of code right here--

component rselect is
port(
b: in std_logic;
e: in std_LOGIC;
fr: in std_logic_vector (3 downto 0);
rz, ro: out std_logic_vector (3 downto 0);
A: in std_logic_vector (2 downto 0));
end component;

component resultsel is
port(
b: in std_logic;
e: in std_logic_vector (3 downto 0);
qz, qo: in std_logic_vector (3 downto 0);
re: out std_logic_vector (3 downto 0));
end component;
component segprocess is
port(
re: in std_logic_vector (3 downto 0);
otL,otR : out std_logic_vector (3 downto 0));
end component;
component Reg is
port(
upd, reset: in std_logic;
f: in std_logic_vector (3 downto 0);
g: out std_logic_vector (3 downto 0)
);
end component;
component sevensegproj is
port(
bcd: in std_logic_vector (3 downto 0);
seg7: out std_logic_vector (6 downto 0)
);
end component;

signal re,Qz,Qo,otL,otR: std_logic_vector (3 downto 0);
signal r0,r1,r2,r3,r4,r5,r6,r7,rz,ro,fr: std_logic_vector (3 downto 0);
signal reset1: std_logic;

--this is where the error is--
RegSelector: rselect port map(A4, e, fr, rz, ro, A);
ResultSelector: resultsel port map(A4, e, qz, qo, re);


entity rselect is
port (
b: IN STD_LOGIC;
e: IN STD_LOGIC;
fr: IN STD_LOGIC_VECTOR (3 downto 0);
rz, ro: out STD_LOGIC_VECTOR (3 downto 0);
A: in STD_LOGIC_VECTOR (2 downto 0));
end rselect;

architecture func of rselect is
BEGIN
process (A,e,fr) begin
if A /= "100" then
if e ='0' then
rz <= fres;
ro <= "0000";
elsif e = '1' then
ro <= fres;
rz <= "0000";
end if;
elsif A = "100" then
if e = '1' then
rz <= fr;
ro <= "0000";
elsif e='0' then
ro <= fres;
rz <= "0000";
end if;
end if;
end process;
end func;


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity resultsel is
port (
b: IN STD_LOGIC;
e: IN STD_LOGIC;
qz, qo: IN STD_LOGIC_VECTOR (3 downto 0);
re: out STD_LOGIC_VECTOR (3 downto 0));
end resultsel;

architecture func of resultsel is
BEGIN
process (e, Qz, Qo) begin
if e ='0' then
re <= Qz;
elsif e = '1' then
re <= Qo;
end if;
end process;
end func;


This is due tomorrow. It all makes somewhat sense to me just don't know why e isn't working when everything else is
 

You didn't post the file sevensegproj.vhd which is where your problem is located.
 

Status
Not open for further replies.
Cookies are required to use this site. You must accept them to continue using the site. Learn more…