[SOLVED] Quad Cross couple PTAT bandgap reference generatorworking principle

"for a stable operation point, the structure needs overall negative DC loop gain"

Not true; positive feedback is okay, as long as it is less than unity.

To illustrate this, consider a system where a positive feedback loop wraps around a stable first-order transfer function, a(jw)=a0/(s/w0+1):



\[a(j\omeg)=\frac{a_0}{s/\omeg_0+1}\]

Let the input be X, and the output be Y. Then,

\[Y=a(j\omeg)(X+Y)=\frac{a_0}{s/\omeg_0+1}(X+Y)\]
\[\frac{Y}{X}=\frac{a}{1-a}\frac{1}{\frac{s}{\omeg_0(1-a_0)}+1}\]

As you can see, the result is a single-pole system with a corner frequency of w0(1-a0). As long as a0<1, this pole remains in the LHP. It will travel to the RHP if a0>1. Also notable, when a0=0.5 this system's gain is 1, and as a0 approaches 1 the gain approaches infinity.

One must be careful to ensure there is no peaking in a(jw)'s transfer function, because if it peaks greater than 1, the loop will go unstable. Some ECG's have this problem--they use shielded wires for noise rejection, but this presents lots of capacitance to a high-impedance source (skin), causing severe attenuation. So they actively drive the shield to the same potential as the signal, reducing the effective capacitance and increasing the circuit's frequency range, but this introduces the possibility of instability. To solve this, the shield buffer's gain is reduced to slightly sub-unity (thus, not fully canceling the capacitance but still canceling most of it). Care must be taken to prevent any frequency peaking in the active shield's driver.

There's apparently a misunderstanding, I'm not referring to poles and frequency domain behaviour, just simple DC operation point.

As far as I see, negative DC loop gain is a prerequisite for a stable operation point with most feedback circuits. The present circuit has it, however.

"There's apparently a misunderstanding, I'm not referring to poles and frequency domain behaviour, just simple DC operation point."

Well, to understand stability we must look at frequency-domain behavior... I remember (before I understood frequency response) flipping the inputs on an op-amp to see if the math equations would show instability, but the result was the exact same equation that I arrived at with the correct polarity. It is only when you consider the op-amp's delay that instability is shown.

"As far as I see, negative DC loop gain is a prerequisite for a stable operation point with most feedback circuits."

Yes, and this is because most feedback circuits have high loop gain. As you can see in the feedback loop I presented, however, the gain isn't negative anywhere yet it is still stable.

"The present circuit has it, however."

I don't yet see a negative DC loop gain... Maybe something I'm missing.

Yes, and this is because most feedback circuits have high loop gain. As you can see in the feedback loop I presented, however, the gain isn't negative anywhere yet it is still stable.

Click to expand...

I agree that you can achieve a stable operation point with positive DC loop gain < +1. It may be necessary to adjust the external bias to keep the operation point out of saturation.

I don't yet see a negative DC loop gain... Maybe something I'm missing.

Click to expand...

A detail analysis shows that it's a multi loop feedback circuit. Marking the gain pathes by the base nodes, you have Q3 in parallel to Q4 and Q2 in series. Q1 acts as a simple level shift. Due to the Q4 degeneration, the positive Q3 gain path outdoes the negative Q4 gain. Thus a positive gain of the parallel circuit gives overall negative loop gain when cascaded with negative Q2 gain.

A detail analysis shows that it's a multi loop feedback circuit. Marking the gain pathes by the base nodes, you have Q3 in parallel to Q4 and Q2 in series. Q1 acts as a simple level shift. Due to the Q4 degeneration, the positive Q3 gain path outdoes the negative Q4 gain. Thus a positive gain of the parallel circuit gives overall negative loop gain when cascaded with negative Q2 gain.

Click to expand...

Okay, I think I see what you're saying. I didn't understand this at first, so I followed a different path and came to a similar conclusion. An alternate explanation is:

Cut the wire linking Q2's base to the rest of the circuit and feed a voltage signal to Q2. The resulting signal at Q3's emitter will indicate the loop gain.

Q2's collector voltage will be -v_i*g_m2r_o2. This signal is then sent in two directions: to Q4's base directly, and to Q3's base (through Q1 acting as a level shift, which for AC signals means no change). The contribution to the output due to Q3 acting as a voltage follower is -v_i*g_m2r_o2. The contribution due to Q4 is from Q4's current gain feeding Q3's emitter resistance, thus +v_i*g_m2r_o2*g_m4/g_m3. The resulting voltage at Q3's emitter, then, is v_i*g_m2r_o2(g_m4/g_m3-1). Since g_m4<g_m3 due to Q4's emitter degeneration, the resulting loop gain is negative.

Thanks for the insight.

Cut the wire linking Q2's base to the rest of the circuit and feed a voltage signal to Q2. The resulting signal at Q3's emitter will indicate the loop gain.

Click to expand...

Yes that how I measured loop gain in a simulation.

If you don't recognize the multi-path structure, you'll possibly try to measure loop gain at Q4 base. You get a positive number < 1, in so far the result indicates stable behaviour. But it's not the overall loop gain.