aleenathomas
Newbie level 3
Hi..
Im trying to implement QPSK modulator and demodulator in FPGA using verilog. In the QPSK demod, first I multiply the QPSK signal with Sine values(Q channel) and Cosine values (I channel) stored in Look Up Table, then give it to integrator where summation with previous inputs are done. Then the sign bit of the values(Decision block) are considered, and are given to a Multiplexer where serial to parallel conversion is being done.
The problem is that the demodulated signal is not matching the modulation signal. Is it necessary to put some threshold values on the output of the Decision block other than considering the Sign bit. I have cross verified the codes I had given, but couldn't sort out the issue. Any help would be much appreciated. As the project submission date is nearing, I'm much worried..
thanks in advance
Aleena:|
Im trying to implement QPSK modulator and demodulator in FPGA using verilog. In the QPSK demod, first I multiply the QPSK signal with Sine values(Q channel) and Cosine values (I channel) stored in Look Up Table, then give it to integrator where summation with previous inputs are done. Then the sign bit of the values(Decision block) are considered, and are given to a Multiplexer where serial to parallel conversion is being done.
The problem is that the demodulated signal is not matching the modulation signal. Is it necessary to put some threshold values on the output of the Decision block other than considering the Sign bit. I have cross verified the codes I had given, but couldn't sort out the issue. Any help would be much appreciated. As the project submission date is nearing, I'm much worried..
thanks in advance
Aleena:|