cupoftea
Advanced Member level 5
Hi
We are doing a 130W offline 100-265VAC, 2 tran fwd SMPS.
130kHz, Ns/np=0.543, Lp = 2.3mH, 24Vout, No PFC.
Not sandwich wound.
Pri FETs are ST18N60
The turn-on switching loss is pretty low since with L(Leak) primary
= some 20uH, it takes 145ns for the primary current to rise to I(pedestal) value of 1.6A.
By this time, the FET gate(s) have been well charged up to Vgs(th)….and even the miller plateau
is a maximum of 59ns, and all this with a UCC27517 gate driver and 33R of added gate
resistance to the lower FET.
The miller charge time is by far the longest time interval of the turn-on switching loss.
It is during this time that most of the (albeit low) switching losses will occur.
So, anyway, as you know, the Crss value cannot be used to calculate the Miller charge time,
since the Crss value is highly variant with voltage.
One must use the Qgd value. (do you agree?)
For the ST18N60 FET, the Qgd is stated as 11.3nC, -but from conditions of 480V and 13A.
We require Qgd from conditions of some 330V and 1.8A.
However, the current level just determines what level the miller plateau will be at.
And this is not of importance....what matters is the time for the Cgd to go from V(bus) to
approx. Vgs(th). So anyway, also, Crss doesn't get significant till a few 10's of volts.
so the fact that its quoted at 480V, can simply be used again at our 330V...since there
is virtually no Crss at either of those high voltages anyway. (330V or 480V)
So do you concur with this?...ie, that we can just use the Qgd value even though we are at 330V and not 480V?
Generally speaking, with any hard switched offline converter, the gate resistor should be sized so that the miller plateau is some
50ns in duration. Would you concur with this? (Any faster and noise problems may get into the control.)
STF18N60
UCC27517
We are doing a 130W offline 100-265VAC, 2 tran fwd SMPS.
130kHz, Ns/np=0.543, Lp = 2.3mH, 24Vout, No PFC.
Not sandwich wound.
Pri FETs are ST18N60
The turn-on switching loss is pretty low since with L(Leak) primary
= some 20uH, it takes 145ns for the primary current to rise to I(pedestal) value of 1.6A.
By this time, the FET gate(s) have been well charged up to Vgs(th)….and even the miller plateau
is a maximum of 59ns, and all this with a UCC27517 gate driver and 33R of added gate
resistance to the lower FET.
The miller charge time is by far the longest time interval of the turn-on switching loss.
It is during this time that most of the (albeit low) switching losses will occur.
So, anyway, as you know, the Crss value cannot be used to calculate the Miller charge time,
since the Crss value is highly variant with voltage.
One must use the Qgd value. (do you agree?)
For the ST18N60 FET, the Qgd is stated as 11.3nC, -but from conditions of 480V and 13A.
We require Qgd from conditions of some 330V and 1.8A.
However, the current level just determines what level the miller plateau will be at.
And this is not of importance....what matters is the time for the Cgd to go from V(bus) to
approx. Vgs(th). So anyway, also, Crss doesn't get significant till a few 10's of volts.
so the fact that its quoted at 480V, can simply be used again at our 330V...since there
is virtually no Crss at either of those high voltages anyway. (330V or 480V)
So do you concur with this?...ie, that we can just use the Qgd value even though we are at 330V and not 480V?
Generally speaking, with any hard switched offline converter, the gate resistor should be sized so that the miller plateau is some
50ns in duration. Would you concur with this? (Any faster and noise problems may get into the control.)
STF18N60
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UCC27517
UCC27517 data sheet, product information and support | TI.com
TI’s UCC27517 is a 4-A/4-A single-channel gate driver with 5-V UVLO and 13-ns prop delay in SOT-23 package. Find parameters, ordering and quality information
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