Q01 – Voltage to Phase Shift?

[KerimF]

Let us assume we have a squarewave of period T=2us (500 KHz) and a voltage (Vctrl) which could vary from 1.5V to 3.5V (2.5V -/+ 1V).

Is there a simple analog circuit which can delay this squarewave 150ps to 350ps (250ps -/+ 100ps) by Vctrl?

Thank you.

Kerim

 

[KerimF]

I wonder why I couldn’t have any idea about it by searching.

I am afraid there will be one way to find a suitable solution for it... by thinking out of the box.

 

[BradtheRad]

It would be easier if your spec delay time were longer. Pico-seconds are difficult to work with.

There are ways to arrange a diode-capacitor-resistor so as to turn incoming square waves into an assortment of different wave shapes...
Upward ramp, downward ramp, sudden drop or rise, plateau or mountain-peak...

You might experiment with these configurations and obtain a waveform you can work with. Then apply Vctrl to level-shift. Then feed it to a Schmitt trigger. Output is a delayed pulse.

 

[KerimF]

It would be easier if your spec delay time were longer. Pico-seconds are difficult to work with.

There are ways to arrange a diode-capacitor-resistor so as to turn incoming square waves into an assortment of different wave shapes...
Upward ramp, downward ramp, sudden drop or rise, plateau or mountain-peak...

You might experiment with these configurations and obtain a waveform you can work with. Then apply Vctrl to level-shift. Then feed it to a Schmitt trigger. Output is a delayed pulse.

Thank you for commenting.
The reason I am interested in achieving this controlled delay is related to the thread:
https://www.edaboard.com/threads/pr...suppressed-carrier-dsb-sc-demodulator.406450/

On its attached schematic, R7 and C5 (at CD4066) delay the squarewave, F_carrier (the recovered suppressed carrier), to compensate the loop error phase which is 1/8 of the carrier period (Tc) in this DSB-SC demodulator (when vco_in=2.5V, the suppressed carrier frequency equals half the VCO one). But, during the lock state, this error phase could have a value between 0 and 45 degrees, 0 to Tc/4, when the carrier frequency or the VCO mid-frequency shifts from its nominal frequency (here 455 KHz, the AM IF and 910 KHz respectively). This affects (decreases) the synchronous detection gain of the recovered audio signal.
Speaking practically, this gain variation (if it happens) is usually not noticed in a voice transmission (I used the DSB-SC system in the 80's for many years in my private short-range RF links).

I mean, this is about a problem to solve for a real situation. It may have no solution, but I keep thinking about it. It is somehow important for the coming Prj02 "Quasi-Stereo FM AM DSB-SC Demodulator".

Kerim

 

[FvM]

Many ways to make a variable delay, e.g. this one https://www.edaboard.com/threads/current-starved-inverter-as-delay-element.406154/

--- Updated Mar 31, 2023 ---

A CMOS inverter with variable supply voltage can also do the trick.

 

[KerimF]

Many ways to make a variable delay, e.g. this one https://www.edaboard.com/threads/current-starved-inverter-as-delay-element.406154/

--- Updated Mar 31, 2023 ---

It seems that this solution is good if integrated. So I wonder if it is also practical to apply it in the special case which I mentioned on post #4 (using standard ICs and discrete components).

A CMOS inverter with variable supply voltage can also do the trick.

This seems a practical solution. But it needs a close study of its non-linearity perhaps, besides its interfacing at its input (a CMOS output of a flip-flop) and at its output (an input control pin of a CD4066 switch).

For instance, do you think there is a model of a CMOS inverter which includes this 'natural' characteristic so that it could be simulated? I usually run the LTspice simulator.

 

[FvM]

There are SPICE vendor models of CMOS gates, e.g. from Nexperia.

 

[KlausST]

Hi,

It seems that this solution is good if integrated. So I wonder if it is also practical to apply it in the special case which I mentioned on post #4 (using standard ICs and discrete components).

Standard IC? What is a standard IC?
Standard LOGIC ICs? I don´t know any that are able to produce a delay as small as 150ps.
You mentioned them, so did you do a research about delay times of standard ICs?

Klaus

 

[KerimF]

There are SPICE vendor models of CMOS gates, e.g. from Nexperia.

Hi FvM,

I believe this helps if I have the privilege to contact SPICE vendors and buy models

Kerim

--- Updated Mar 31, 2023 ---

Hi,



Standard IC? What is a standard IC?
Standard LOGIC ICs? I don´t know any that are able to produce a delay as small as 150ps.
You mentioned them, so did you do a research about delay times of standard ICs?

Klaus

Hi,

I am very sorry for not being clearer.
I meant that the required controlled delay is needed in a project like "A Simple Reliable Double Sideband Suppressed Carrier (DSB-SC) Demodulator" (mentioned on post #4) in which standard ICs (CD4046B, CD4066B, CD4013B and LM339) are used.

Kerim

 

[KlausST]

Hi,

I still don´t understand. In post#4 you also talk about frequencies below 1MHz.
This means more than 1us = 1,000ns = 1,000,000 ps.

The CD4066 datasheet talks about delay of typ 20ns up to 40ns (@10V). You see there are several ns of uncertainty.
20ns equals to 20,000ps.

But you talk aboutthe delay of 150ps to 350ps ... which is way overruled by the uncertainty of an CD4066.

I don´t understand how all these numbers fit.

Klaus

 

[KerimF]

Hi,

I still don´t understand. In post#4 you also talk about frequencies below 1MHz.
This means more than 1us = 1,000ns = 1,000,000 ps.

The CD4066 datasheet talks about delay of typ 20ns up to 40ns (@10V). You see there are several ns of uncertainty.
20ns equals to 20,000ps.

But you talk aboutthe delay of 150ps to 350ps ... which is way overruled by the uncertainty of an CD4066.

I don´t understand how all these numbers fit.

Klaus

I see now, and you are right.

As you know, we usually start to analyze a new circuit by assuming its devices are somehow ideal, like using models in a simulator with typical characteristics (of interest). If the circuit seems working well, we go further to more detailed analyses, step by step, in every part of the circuit. Even if the results of the simulated circuit seem being good as required, building and testing the circuit in real likely take us to more studies about how to make it practical and reliable while using real devices.

The new main circuit here is the DSB-SC modulator (assumed non-existent universally). When its PLL is in its lock state, there is a phase (delay) between the recovered suppressed carrier (VCO out / 2) and the transmitted one. The medium value of this phase difference (the PLL error phase which produces the lock) is 45 degrees (or 275ns in case of 455 KHz, AM IF). If the frequency of the suppressed carrier is not equal to the VCO mid one (divided by 2), this phase could vary from 0 to 90 degrees (extreme limits before the loss of synchronization). In the basic circuit of this demodulator, the phase difference is compensated approximately by R7 (10K) and C5 (100n) which gives a fixed delay. But this delay, as you pointed out, includes the propagation delays of CD4013B and CD4066B which are also in ns.

I just thought if I can add something to R7 and C5 to let the delay track the instantaneous voltage of VCO_in (after being buffered and filtered properly) so that the gain of the synchronous detector (CD4066 switch) could be made to be somehow constant.

For instance, in the 80's, I deliberately let the frequency of my suppressed carrier vary at a rate of about 6 Hz in a rather wide band (say 1 MHz +/- 30 KHz, on MW band). This let the listeners of the conventional MW receivers hear a sort of noisy on-off interference (since the transmission covered many MW channels) while a voice signal was transmitted properly (it was a sort of scrambling method). Even with the fixed delay, the variation of the synchronous detector gain wasn't noticeable during a conversation.

Anyway, in these days, this is just an academic study (not taught at any university around the world) since FCC doesn't recommend the use of the DSB-SC system.

Regards,
Kerim

 

[KlausST]

Hi,

I understand the 275ns

But then you talk about a 10k, 100nF combination which is about 4000 times that much in delay.
You're not close at the same area.

Klaus

 

[KerimF]

Hi,

I understand the 275ns

But then you talk about a 10k, 100nF combination which is about 4000 times that much in delay.
You're not close at the same area.

Klaus

Ooops... I guess I need new glasses. 100nF is actually 100pF
And while, in this case, T=RC=1000ns seems high, the actual delay is much shorter (about /4) due to the narrower voltage band of the C charge/discharge. This could be seen on the simulator.

Thank you for notifying me about this mistyping (though it seems it can no more be corrected above, post #11).

Kerim

 

[BradtheRad]

At the speed of light, 250 pSec delay is a fraction of an inch. Theoretically you can touch two wires together at different points along their length, to obtain any range of delays.

Or turn on any of a series of transmission gates at points along a wire, to obtain the delay.
Since you mention using a 4066 IC, here's a CMOS transmission gate found in Falstad's simulator circuit library. The control wire is interactive user switchable (Hi or Lo) during a run.

 

[KerimF]

At the speed of light, 250 pSec delay is a fraction of an inch. Theoretically you can touch two wires together at different points along their length, to obtain any range of delays.

Or turn on any of a series of transmission gates at points along a wire, to obtain the delay.
Since you mention using a 4066 IC, here's a CMOS transmission gate found in Falstad's simulator circuit library. The control wire is interactive user switchable (Hi or Lo) during a run.

Sorry, I couldn't get you well,
I mean, I can't see the DC controlling voltage by which a delay could be varied from about 150ns to 350ns.

For instance, I wish you know that I have no more the privilege to download (for free or paid) any simulator (besides many other engineering tools for hardware or software) due to world's regulations. So, I was fortunate for downloading the professional simulator, LTspiceIV, many years ago

 

[BradtheRad]

I can't see the DC controlling voltage by which a delay could be varied from about 150ns to 350ns.

As you say, changing the wire length doesn't offer an easy method to vary the delay.

In order to do it electronically and rapidly It may be necessary to invent a new component. Or a novel usage of components.

Some schematics have a few logic gates in series for no other purpose than to introduce a small time delay.

Here's a Youtube video illustrating how a 12 inch length of wire creates a nanoSec time delay:

 

[KerimF]

n order to do it electronically and rapidly It may be necessary to invent a new component. Or a novel usage of components.

In this special case when the RC fixed delay is at the input of a CMOS logic (it could be of CD4066 or CD4013), shifting the triangular signal at this input by a positive voltage (higher than 2.5V, via a resistor), the delay is increased (to reach 2.5V) by the negative slope and decreased by the positive one. The inverse occurs if a lower voltage than 2.5V is applied. But this method has a drawback. It also changes the duty cycle of the squarewave.

So, applying this method on R7 and C5 above of the DSB-SC demodulator will also deform the synchronous detector gain. And this is not acceptable. The remedy could be to place the RC delay shifter before CD4013B. The voltage driving the CD4066B will be therefore a squarewave (50% duty cycle) always, no matter what the duty cycle at the clock input of the CD4013B is.

Again, the drawback of the updated delay method is that the slopes of the delayed triangular voltage on C are halved (frequency is doubled) which will likely produce more delay's jitter in a real circuit (not on the simulator). Is that jitter acceptable or not, speaking practically? This can be known by a test on a real board.

I am sure it will be acceptable in the special 'voice' transmission (FM AM DSB-SC system in which the amplitude and the frequency of the suppressed carrier are modulated by two different audio signals simultaneously). I said, I am sure, because even with a fixed delay that let the detector gain change with the PLL error phase (in case the carrier frequency is also modulated), the received voice signal sounded normal (tested in real).

May I say that the purpose of this thread reached its end?
The various ideas presented here are also very interesting. They are certainly useful and applicable in some other applications.

Best regards,
Kerim

 

[KlausST]

Hi,

I´m so confused. Every post gives new - to me random - informations.
Picoseconds, nanoseconds, picofarads, nanofarads ... I don´t know what is valid now.

Now in post#17 you talk about a "triangular signal" ... where does this come form. Never mentioned before..
And how do you want to "shift it with a resistor"?
And how can it "change the duty cycle of the square wave"? The only "square wave signal" in the above posts is the input.

May I say that the purpose of this thread reached its end?

At least for me.
I may come back if there is a new (single) post giving all requirements and informations, also very useful: signal diagrams with timing informations, schematic sketches.. and so on.... (Verify the data before posting!)

Klaus

 

[KerimF]

I´m so confused. Every post gives new - to me random - informations.
Picoseconds, nanoseconds, picofarads, nanofarads ... I don´t know what is valid now.

Now in post#17 you talk about a "triangular signal" ... where does this come form. Never mentioned before..
And how do you want to "shift it with a resistor"?
And how can it "change the duty cycle of the square wave"? The only "square wave signal" in the above posts is the input

The new main circuit here is the DSB-SC modulator (assumed non-existent universally)

Hi,

It seems you didn't notice yet when I started here talking on applying the delay shift on the circuit (on which R7 and C5 exist) which I posted earlier on the thread:
https://www.edaboard.com/threads/pr...suppressed-carrier-dsb-sc-demodulator.406450/

So as long you will not have time to have a good idea of the DSB-SC demodulator, I presented, I am afraid we will keep talking by a river while walking on its separate sides.

When I personally open a thread, I usually start a study in progress, no matter if I do it with a question or an innovative idea. My threads won't be limited by the first post only because I can't predict what others may know (or not know) from the beginning. But I also understand that perhaps there is also a rule not to that.

Kerim

 

[KlausST]

Hi

It seems you didn't notice yet

So as long you will not have time to have a good idea

Sorry, my fault to not understand your informations .. and that i can´t follow your switching topics.

I won´t bother you again.

Klaus