Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Q: What is the difference between Jitter and Skew?

Status
Not open for further replies.

compengg

Newbie level 4
Newbie level 4
Joined
Oct 20, 2006
Messages
5
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,310
difference between skew jitter

Can someone please explain the difference between Jitter and Skew. What problems they can cause and how each of them can be tackled?
 

difference between jitter & skew

"Clock Basics"
**broken link removed**

Regards,
IanP
 

different between clock jitter and skew

Skew is due to delay in the clock to gate in a synchronous systme
in clock skew the clock varies spatially.
Jitter is due manufacturing defects.
 

the difference between skew and jitter

Skew is an unwanted delay during the propagation lines between the clock source and clock destination. Search for "RoboClock" at https://www.cypress.com.
or for "clock syntesizer" at https://www.ti.com
Solving skew problems with PLL based circuits are usually adding phase noise (jitter) to a clean signal generator (-145dBc) destroying the pase noise parameter (down to -90dBc).
Jitter and skew are two corelated problems. Trying to remove one you're creating (more or less) the other.
 
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top