PWM creator, and counter

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Paul Wardlaw

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Hi, Ive got a problem where I am trying to create PWM's depending on the initials of your name. Its to have 2 pulses for the first initial, and then 2 for the second. And keep getting the error "Can't resolve multiple constant drivers for net "i[2]" i[1] etc. Any advice .....




//Design that will output a signal that will control a small servo
//Length of output pulses are dictated by the users first and second initials
//Looking up the corresponding ASII code for said initials
//Two output pulses (2 high, 2 low) for each inital and then resets.


Code Verilog - [expand]
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module controller (clock, select, PWM_o, count, i);
 
input clock, select;
output reg PWM_o;
output reg [2:0] i = 0;
output reg [16:0] count = 0;
 
 
 
always @(posedge PWM_o)
if (PWM_o == 1)                     //Seperate counter that counts the amount of output pulses
begin                               //2 Pulses of each initial needed
    i=i+1;
end
 
 
always @(posedge clock)
begin
    count <= count+1;               //Counter matches the input clock frequency, used to control the output pulses
end
                        
                        
 
always @(posedge count)
begin
if (select == 1)                    //Select chooses the PWM, 1 for Uppercase letters, 0 for Lowercase
    begin   
        if (i<2)                    //Sets up loop conditions for first initial, so we get 2 pulses 
            begin           
                if (count < 65617)  //Conditions for output wave, resulting in 2 pulses of 1.31ms       
                    PWM_o <= 0;         
                else        
                    PWM_o <= 1;                         
            end         
        else                
            begin           
                if (count < 67024)  //Conditions for output wave (pulse 2),second inital        
                    PWM_o <= 0;         
                else        
                    PWM_o <= 1;                             
            end 
                if (i==4)           //If 4 pulses have been completed, resets and starts pulsing again
                    begin       
                        i = 0;          
                    end         
    end
else                                //If select = 0, lowercase initials are used
    begin   
        if (i<2)                    //Sets up loop conditions for first initial, so we get 2 pulses 
            begin           
                if (count < 72046)  //Conditions for output wave, resulting in 2 pulses of 1.44ms       
                    PWM_o <= 0;         
                else        
                    PWM_o <= 1;                         
            end         
        else                
            begin           
                if (count < 72993)  //Conditions for output wave (pulse 2), second initial      
                    PWM_o <= 0;         
                else        
                    PWM_o <= 1;                             
            end         
                if (i==4)           //If 4 pulses have been completed, resets and starts pulsing again
                    begin       
                        i = 0;          
                    end 
    end                                 
end
 
endmodule
 
Last edited by a moderator:

You are assigning values to i in multiple procedural blocks, which isn't allowed.

See. @(posedge PWM_o) and @(posedge count) blocks.

You are using the multi-bit output reg count as a clock, this won't synthesized correctly (should probably result in an error, but I've never tried this). Then you also use the count value in the procedural block that uses count as the clock. This will result in a race condition between the count "clock" and the count used as an input. This is not a good design practice.

You are also using logic to generate clocks if this is to be synthesized in an FPGA that is not a good practice, as access to the clock buffers in FPGAs is limited from the fabric. Everything should be implemented using a single clock domain.

You are also mixing = (blocking) and <= (non-blocking) assignments. You should stick with only using blocking assignments in combinational always blocks (always @*) and non-blocking in sequential always blocks (always @ (posedge some_clock)). Mixing them can result in synthesis/simulation mismatches.

Regards
 


Pretty much this. And since in this design you are using only sequential always blocks (good idea), you should get rid of the blocking assignments you have in there.

That means that things like i=i+1; should be i <= i + 1;. Also note that those two statements are NOT equivalent. The blocking assignments (=) depend on order, and can end you in a fine mess indeed. The non-blocking assignment (<=) do NOT depend on order.

Also, question: what frequency is the clock signal for that controller going to be?
 

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