Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

PWB Design - Soldermask Application and Vias as Test points

Status
Not open for further replies.

sunybeet1987

Newbie level 1
Newbie level 1
Joined
Aug 31, 2011
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,289
My company uses Incircuit Tests as much as possible. Manufacturing Engineering has changed printed circuit board suppliers. The New supplier solders is filling the vias so the test probes are not making contact with circuit. The solder mask does not constantly fill the same vias. There is a requirement to cover all vias under any components. I read some comments about how vias should not be used as ICT Test points and the vias should be covered for production.

My question is what causes the soldermask to fill the vias on standard .062" thick pwb? Why would this happen changing suppliers? Any suggestions for notes to be added to the pwb prints to handle this issue?

Thanks,

Greg
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top