pure input/output/bi-direction pins in the leakage test

Similar threads

• K

  input

  • Started by kimilee
  • Yesterday at 11:59 PM
  • Replies: 0

  ASIC Design Methodologies and Tools (Digital)
• S

  How should I use my self-designed TPG circuit to input test patterns into the test circuit of iscas89 and test its fault coverage in tetramax?

  • Started by sicetn
  • Dec 18, 2023
  • Replies: 0

  ASIC Design Methodologies and Tools (Digital)
• F

  JTAG TDI and TDO pins and its relation with Si and So pins

  • Started by fragnen
  • May 24, 2024
  • Replies: 8

  ASIC Design Methodologies and Tools (Digital)
• Input test vector is not loaded in the Questa

  • Started by mohamis288
  • Feb 16, 2023
  • Replies: 2

  ASIC Design Methodologies and Tools (Digital)
• K

  [SOLVED] When does a flip-flop capture its input

  • Started by keyboardcowboy
  • Jun 28, 2024
  • Replies: 14

  ASIC Design Methodologies and Tools (Digital)