Pulse width of PFD in PLL

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neoflash

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pfd in pll

Hi: In 130nm process, what is the minimum required pulse width of PFD, to avoid the dead-zone.

thanks,
Neoflash
 

Depend on the architecture of your switched current source. If the switched current source could be described by a first order time response take 3-5*time constant.
 

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    neoflash

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that matchs my guess.

And I's thinking why can not make the pulse much wider than necessawy, while guarantee far less than reference clock.
 

i think if the enough delay time in the PFD,the dead zone can be avoid ,
 

no,the delay time will effect other porformances of the PLL.don't keep it too long.
 

bill_sun said:
no,the delay time will effect other porformances of the PLL.don't keep it too long.
Click to expand...

What will be impacted? thanks
 

While the current sources (positive and negative in locked state) is active there is noise current. So the noise contribution from the current source is lower if the duty cycle is smaller.
 

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    neoflash

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yes, noise will inject in to loop filter when cp is open . also, the longer charging time will cause
larger ripple in control line.
 

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