pulse generator (radar) VHDL

Hi all,

i need to write VHDl code to produce a square wave output with an amplitude of 2.8v and duration 2 ms every 100 ms as a simulated radar output. Your help will be much appreciated as my lack of Vhdl coding has become apparent.

Smudge

Is it near hand in time or something?

Not yet but need to get on with it!!

I guess you need a counter to divide the clock, whe the counter reaches certain value, pull up the flag. remember sync the flag signal before you apply the it to control other logic.

smudger_87 said:

Not yet but need to get on with it!!

Click to expand...

THen I suggest you take your own advice and come back when you have specific problems with your code.

I have tried using state machines and counters with a clock divide but have problems synthesising if I try to use a way for statement or use a rising and falling edge statement in the same process. What is the flag counter?

post your code so we can see what errors you have made.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Pulse_outgoing is
Port ( h10z : in STD_LOGIC;
reset : in STD_LOGIC;
pulse : out STD_LOGIC);
end Pulse_outgoing;

architecture Behavioral of Pulse_outgoing is

signal pulse_int: STD_LOGIC_VECTOR (1 downto 0);

begin

process (reset, h10z)
begin

if reset = '1' then
pulse_int <= "00";
elsif (rising_edge (h10z)) then
if pulse_int < "11" then
pulse_int <= pulse_int + '1';
else pulse_int <= "00";
end if;
end if;
end process;


process (pulse_int)

begin

case pulse_int is

when "00" => pulse <= '0';
when "01" => pulse <= '1';
when "10" => pulse <= '0';
when "11" => pulse <= '1';
when others => pulse <= '0';

end case;
end process;



end behavioral;

I dont see any problems with this code - what problems are you having?

No problems it works but not for what I need my outgoing pulse is well over the 2 ms pulse I need as I want a duty cycle close to 10% not the 70 or 80 this method is giving me. I tried dividing the pulse by 2 but the divide code I tried wouldn't work.

then why not use a faster clock?

entity Pulse_outgoing is
Port ( clck : in STD_LOGIC;
reset : in STD_LOGIC;
pulse : out STD_LOGIC);
end Pulse_outgoing;

architecture Behavioral of Pulse_outgoing is

signal count1 : integer range 0 to 100000 := 100000;
signal count2 : integer range 0 to 49000000 := 49000000;
type state is (s1,s2);
signal current: state :=s1;

begin

process (clck, reset)

begin

if (clck'event and clck = '1') then

case current is

when s1 =>

if (count1 = 100000) then
current <= s2;
count1 <= 0;
else count1 <= count1 +1;
pulse <= '1';
end if;

when s2 =>

if (count2 = 49000000) then
current <= s2;
count2 <= 0;
else count2 <= count2 +1;
pulse <= '0';
end if;


when others => null;
end case;

end if;
end process;

end behavioral;

next one im trying except now my outgoing pulse produces nothing when testbench.

smudger_87 said:

No problems it works but not for what I need my outgoing pulse is well over the 2 ms pulse I need as I want a duty cycle close to 10% not the 70 or 80 this method is giving me. I tried dividing the pulse by 2 but the divide code I tried wouldn't work.

Click to expand...

You don't want 10% you want 2ms out of 100ms so it's 2%. What you originally wrote with the four states was a 50% duty cycle pulse. if you want 2% you'll have to have at least 50 counts with only 1 count being the pulse.

The clock will have to have a 2ms period.

I get the impression you're not a HW type.

Nope not at all lets say I'm more comfortable with physical engineering not programming. But thanks for the reply!