A clock signal has a fixed high time and a fixed low time (together constitutes a clk period) which keeps repeating.
As per my knowledge this is the definition of a pulse - A rapid, transient change in the amplitude of a signal from a baseline value to a higher or lower value, followed by a rapid return to the baseline value. It mostly has a high time and we may not know in advance when the high time will occur.
I have taken for granted here that the pulse is non-repeating (because you have written "I have one pulse signal").
So can you please clarify what is meant by frequency and period of a pulse (your pulse)?
if a periodic pulse has a known width and repetition rate and you wish to synchronize a clock to this pulse rate, a PLL chip such as CD4046 using Type I XOR mixer if VCO is close to required frequency and filter bandwidth allows capture range required.
If working to 1ns pulses, then special microwave or CML parts are needed.
Anything above 300MHz can be considered UHF to microwave such as 2ns cycle or 500MHz.
As others have pointed out, a very high speed clock is needed!
The above person has already given you a very brief idea. Detect when you have the rising-edge of the pulse, immediately start incrementing a counter using a very high speed sys clk (I am sure you can calculate this yourself), then stop counting when you detect the falling-edge of the pulse. Store the count value and then generate a signal which will toggle states at this count value. You'll have your continuous signal with T=2ns (replicating your 1ns high pulse).
Do you want to do in in ASIC or FPGA or on a board with connected components?
Getting a system clock >500MHz can be a concern.