Pull down not working on 74LS192 counter

dvalero484

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Hello.

I've been working on a digital clock with alarm.

For the alarm, I'm using 74LS192 0-9 counter and a 7448 decoder, as shown in the picture. For the clock, I made a pull-down with a 1k resistor. However, it won't count whenever I press the button, but if I use a logic state or a clock generator for the clock, it works. I've been watching videos and I have the exact same as them. Can't figure this out. Why does this happen and how can I solve it?

Thank you.

PD: I changed the pull down for a pull up and it worked (sending high value when I stop pressing the button and low value when pressing it, of course) any idea why?
 

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Hi,

the shown schematic should work.

(but indeed your description is not clear. You said you modified something and tested several ways ... and thus I´m not sure which version your schematic shows. )
Be sure to show the "not working" schematic.

For further debugging you could place a level indicator directly at the UP line.

****
Mind: IDLE level of UP and DOWN should be HIGH (according datasheet). Thus I recommend to do so.
Again: still your circuit like shown should work.

Klaus
 

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Real 74LS logic input will recognize 1k pull-down as low level (input source current max. 0.4 mA, low threshold min. 0.8 V).

In this mixed mode simulator, digital signals are treated specially, apparently a simplified level detection algorithm is used. Using pull-up and switch to ground is standard method for 74 and 74LS (respectively has been 50 years ago) and should be supported by the simulator.
--- Updated ---

Correction, 74LS192 input recognizes pull-down up to 2k as low level in Proteus. No idea what you did.
 
Last edited:

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Thanks for replying.

The schematic shown is the one with the pulldown that doesn't work (but it should), it only works with a pull up, for some reason I don't know yet. I got it working with a pull-up, but I need to know why pull-downs are not working on this one.

By the way, when using pull-down it does sends high and low values to the clock, but doesn't count
 

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I've looked at the data sheet at https://www.ti.com/lit/ds/symlink/s...90133&ref_url=https%3A%2F%2Fwww.google.com%2F.
Page 5 shows how the input signals operate. It clearly shows that the default state for the 'up' and 'down' pins is high and the operation occurs when the signal transitions from low to high.
Also 'Note B' at the bottom of that page states that for either the up or down signals to work, the other must be high.
(It always pays to read and understand the datasheet.)
Susan
 

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Aussie Susan said:
Also 'Note B' at the bottom of that page states that for either the up or down signals to work, the other must be high.
Click to expand...
That's the case in shown schematic.
dvalero484 said:
By the way, when using pull-down it does sends high and low values to the clock, but doesn't count
Click to expand...
Interesting, you should have mentioned this earlier.

Clock input has also dynamic requirements like maximal signal risetime. Triggering a counter by a pushbutton isn't reliable in real hardware because it involves bouncing.
 

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Thank you for taking some of your time for helping me.

Sorry if I'm wrong (I'm new at this, as I'm just taking this subject in the university) but shoudn't it work anyways? With the only difference that with a pulldown it'll transition when pressing the button, and with a pullup will transition when releasing it?

Take a look at this video (video's in Spanish):


This person's using a pulldown for the clock, and it works perfectly, and down signal's not even high when only using up signal.

I really appreciate you for helping me.
 

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FvM said:
That's the case in shown schematic.
Click to expand...
Sorry - I mistook the downward facing symbol on the 'DN' pin as a ground.

Is this a real circuit or a simulation (as in the video)? In my opinion, simulators only go so far and they can be very misleading. With real switches, contact bounce needs to be take into account.
Also check out what @FvM says about the dynamic characteristics.
Susan
 

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Hi,

dvalero484 said:
This person's using a pulldown for the clock, and it works perfectly, and down signal's not even high when only using up signal.
Click to expand...
The video may be fake .. or the simulator does not work like the real part.

--> What you can and should rely on is the datasheet. Don´t trust any second sources more than the datasheet.
As already mentioned by me and others: The UP and DN signals need (according datasheet) be HIGH on IDLE.


Klaus
 

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Other than reported by the OP, I see 74L192 counting in the given circuit with 1k pull-down. Checked with Proteus 8. Which version are you using?
 

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74XX and 74LSXX TTL design is now obsolete, but one design rule (not followed by all designers!)
is to never connect inputs directly to VCC.
Either leave them unconnected or use a series resistor to VCC.
The reason is that the absolute maximum voltage for VCC is 7V, but it is only 5.5V for inputs.
This means that the absolute maximum VCC is reduced to 5.5V if any input is directly connected.
You want to keep the margin from operating voltage to the absolute maximum voltage.
 

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I guess that you started digital logic design before 74LS was widely used (me too). 5.5V maximum input voltage applies to standard 74 and fast 74S series. 74LS has 7 V maximum input and VCC rating.

 
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Hi,
std_match said:
is to never connect inputs directly to VCC.
Either leave them unconnected or use a series resistor to VCC.
Click to expand...
nowadays most parts are CMOS.
With CMOS: never let an (used or unused) input unconnected (unless noted otherwise)
And the datasheets usually give their specificatons with "Inputs connected to GND or VCC". (not mentioning a resistor)

Sill I agree that with the 74xx or 74xx devices it was somehow different. It simply was a different technology.

In the end .. I don´t think it is not the cause of the OP´s problem, since the OP uses a simulation tool.

Klaus
 
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All TTL `also operate with no input = "1" (yet should not for immunity reasons) The input currents for "0" being much higher require a smaller resistor than 10k pullup.
0.4mA * 2k = 0.8V the defacto limit for std design but not the actual threshold of 0/1..

The floating input voltage tells you the threshold is two PN or Vbe drops of 0.65*2 as seen by analyzing all schematics for TTL.
The 0.8 and 2V input thresholds are for equal noise power margin of 240 uW =(Vh- Vt)*I from the 1.4V threshold at some temperature.

Perhaps you have a std. 74 power TTL chip. (they still teach this?)
 

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A series resistor can sometimes be useful also with current hardware technologies.
It makes it easy to override the input, for testing or debugging.
 

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