PTM and MOSIS process technologies

[aindejeje]

Help Me. Basic of PTM technology.

Hi all,

Previously i used process technologies from Mosis for my simulation.
It already has test result for every technologies.
Now im migrating to PTM model.
Im looking for minimum dimension for 90nm, 65nm, 45nm and 32nm technology.

From IBM test result (130nm), the Lmin=0.12u, and Wmin=0.16um
It there any way to determine the Wmin?

And how can i find λ, µ, and γ for PTM?

Thanks for your help!

 

[analogLow]

Re: Help Me. Basic of PTM technology.

>From IBM test result (130nm), the Lmin=0.12u, and Wmin=0.16um. It there any way to determine the Wmin?
Yes, a simple way is to use a technology scaling model. I typically use the model presented in Digital Integrated Circuits: A Design Perspective by Rabey, Jan M (2nd edition). See table 3-8 on p.124.

Using this model for to find W for the 32nm process would give a scaling factor S =Lmin,old / Lmin,new = (130nm) / (**32nm)= 3.75
Then you can solve for Wmin,32nm = (Wmin,130nm)*(1/S) = (0.16um)/(1/3.75) = 0.0427e-06. This gives a smaller W which is what we expect.

**this value may be smaller by a few nm.
>And how can i find λ, µ, and γ for PTM?
You may apply the same technique above for some of these values but some may be only found from foundries that make those technologies. I would recommend looking through IEEE papers.

Cheers,
analogLow

 

[erikl]

Re: Help Me. Basic of PTM technology.

From IBM test result (130nm), the Lmin=0.12u, and Wmin=0.16um. It there any way to determine the Wmin?

You can also find Wmin values for 90 & 65nm processes in the MOSIS Wafer Electrical Test Data and SPICE Model Parameters sections. Also (Spice-adapted) mobility values.

 

[aindejeje]

Re: Help Me. Basic of PTM technology.

>From IBM test result (130nm), the Lmin=0.12u, and Wmin=0.16um. It there any way to determine the Wmin?
Yes, a simple way is to use a technology scaling model. I typically use the model presented in Digital Integrated Circuits: A Design Perspective by Rabey, Jan M (2nd edition). See table 3-8 on p.124.

Using this model for to find W for the 32nm process would give a scaling factor S =Lmin,old / Lmin,new = (130nm) / (**32nm)= 3.75
Then you can solve for Wmin,32nm = (Wmin,130nm)*(1/S) = (0.16um)/(1/3.75) = 0.0427e-06. This gives a smaller W which is what we expect.

**this value may be smaller by a few nm.
>And how can i find λ, µ, and γ for PTM?
You may apply the same technique above for some of these values but some may be only found from foundries that make those technologies. I would recommend looking through IEEE papers.

Cheers,
analogLow

Thanks for the equation and explanation.
Can you provide me specific link for IEEE papers to this issue.

You can also find Wmin values for 90 & 65nm processes in the MOSIS Wafer Electrical Test Data and SPICE Model Parameters sections. Also (Spice-adapted) mobility values.

I found the minimum sizing (Wmin:Lmin) from IBM for:
130nm = 0.16um:0.12um
90nm = 0.12um:0.10um
65nm = :0.12um:0.06um

IMO, this is the practical value.
thanks.

 

[analogLow]

I got the equations from this textbook:
Amazon.com: Digital Integrated Circuits (2nd Edition) (9780130909961): Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic: Books

However, you if search for "technology scaling factor CMOS" on the web, you can find almost the same information.

Cheers,
analogLow