PSRR simulation for LDO

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How to do PSRR simulation for LDO in cadense?
 

set the ac value of the supply to 1 and run ac simulation and monitor the output of the LDO
 

i think you will find psrr-shap is opposite to open loop gain
 

Yes ... the shape is almost the same as that of ur loop gain...

I fact the psrr curve of regulator can be divided in three regions..
1) in the first part the psrr i dominated by the psrr of bandgap... till the cut off freq of b'gapfilter.
2) in the second halffrom cut off of the b'gap to the ugf of loop... the psrr is dominated by loopgain of regulator.
3)and after that once the loopgain is out the output cap holds the forte... which is finally saturated by the pesence of ESR.

you can find a more detailed description on this at ti.com... in the analog journal.
 


Well !
By this classification ,I think a 4th region could occur where PSRR is minimum ;it is at which all of the three fail to dominate (Band gap , regulator loop , out cap)

ashish_chauhan said:
in the first part the psrr i dominated by the psrr of bandgap... till the cut off freq of b'gapfilter.
Click to expand...
Do you mean that at the following region the PSRR degrades due to BandGap psrr degradation?
 

you can find a very good paper by vishal mishra and rincon mora which clearly describes the procedure.
 

When you simulate PSRR for LDO, what is the load condition, no load condition or heavy load condition?
 

You should examine all application corners and a
LDO when operated in low-drop regions will see
its gain and frequency response vary widely with
headroom and load. Finding the worst conditions
and then "why?" can be enlightening (or only a
bug hunt). But if you're going to claim it, prove it.
 

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