PSRR Graph analysis

[rshu]

Hi Guys,

I've simulated the PSRR for LDO & got the PSRR graph. Which is quite similar to Gain plot but here i've seen one thing which is after Hitting the peak it again came down.

So anybody can help me to get rid of this why it is happening ?

 

[danadakk]

All amplifiers, and control loops with G in them, experience finite GBW limitations.
That in turn compromises its performance. So in short unless you have infinite energy
to produce an amplifier with infinite GBW you will get declining PSRR in the control loop,
and other noxious problems like Z rises in amplifier output.....

Post your sim file, if LTC or whatever, so rough verification can occur.


Regards, Dana.

 

[rshu]

Thanks for reply Dana,

Actually i'm asking you about this
Here in the picture you see after hitting the Peak it again come down So i just want to know why it is happening. I've circled that in the graph.

 

[FvM]

How about some axis annotation?

 

[rshu]

x axis is in dB ( vsupply/Vout) y axis is in frequency. Its an PSRR graph

 

[danadakk]

Unusual graph, never seen a PSRR curve have a pick, always a LPF
kind of behavior. Then I found this so I am learning as well -

This seems to expalin the phenomina at work : https://www.ti.com/lit/an/slyt202/slyt202.pdf

Can you post sim file ? Is this a circuit sim or a device sim you are doing ?


Regards, Dana.

 

[KlausST]

Hi,

as a guess ... maybe there is a capacitor (intentionally or not) at the output that suppresses high frequency ..

Klaus

 

[danadakk]

From the ap note posted in #6 post -

And ap note discusses other considerations as well.


Regards, Dana.

 

[D.A.(Tony)Stewart]

Low ESR caps always improve the PSRR and cause this -1 order effect.

I am not an expert in this but I believe the so-called capless LDO might not tolerate large cap loads but have exceptionally large GBW compensated internally for lower loop gain to give good phase margin and still meet all requirements of error reduction ( input, supply and step loads). It depends on your specs as output FETs have a limiting RdsOn*Coss = 0.5/fmax (10~90% risetime not 63%) but wide enough variance to choose the best specs and implementation. Too low Cout is also a problem as it both attenuates step load regulation error but also reduces feedback gain and reduces phase margin. I don’t have a solution to these trade offs now, just pointing them out.