Psrr for current mirror

[sneha rayala]

 

[dick_freebird]

Yeah... Hard to decipher, and maybe spend a little more thought on the question?

 

[sneha rayala]

Sure @dick_freebird , sorry for that , I have read somewhere that the bias nets i.e gate terminals in current mirrors are shielded to supply (for PMOS mirror pair) to improve PSRR , and was just thinking if the reason could be that the shielded routing and also bias net routing will experience same voltage swings and so the effective coupling cap seen between them is less and so it will not act like short at high frequencies and improve PSRR

Or in other way could you please make me understand how shielding with supply net for gates of pmos current mirror pair help in improving PSRR

 

[dick_freebird]

This probably is about HF PSRR.

Every transistor on the gate rail is a capacitor to somewhere. Many are to the opposing supply rail (by way of something or other) so supply deflection becomes bias rail deflection and there's your rising-with-frequency "bad stimulus".

"Shielding" is really an element of capacitive division, shunt to the FETs' series-C to the bias rail.

An attendant mitigation is to use cascodes appropriately to block / shunt key "injector" paths' HF energy to a rail by their own Cgs while passing DC (a matter of degree, but PSRR is a team effort against a few bad actors usually, IME).