provide rtl for the descibed design

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sun_ray

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In our design there is an output named ddr_out which is 6 bit wide. We want to send address on this ddr_out at both positive and negative edges of the clock of our design. Can any body provide the synthsizable rtl for this?

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sun_ray,

I get the distinct impression (based on your recent slew of posts) that you want people on the edaboard to do your work for you. Work your employer is paying you to do, based on qualifications that you were supposed to have. Maybe what you need is a job that matches your skill set instead of one that requires skills you don't have. You're recent posts go way beyond requiring on-the-job training and into...I need to take some classes.
 

Agree with ads_ee ...

this forum is for queries where you are not able to resolve your issue ...you are stuck somewhere and you need help ..

sun_ray,
please provide RTL here for your design .. then we can look at your code and can help you in coding that design .. but you need to try first.

Rahul
 

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