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Prototyping system to use DAC spotlight
By Michael Santarini, EE Times
Jun 2, 2003 (8:06 AM)
URL: **broken link removed**
San Mateo, Calif. - Monterey Design Systems will preview its Calypso silicon virtual prototyping system at the Design Automation Conference this week.
Monterey created the tool by merging its Sonar physical-synthesis tool with the IC Wizard design planner gained when it acquired Aristo Technology Inc. Built atop a hierarchical database, the tool combines hierarchical design planning, physical synthesis and physical prototyping. It replaces the individual IC Wizard and Sonar tools.
Dave Reed, vice president of marketing at Monterey (Sunnyvale, Calif.), said Calypso is the first tool to take designers from pre-RTL physical prototyping through to placement of optimized gates.
"When design architects are drawing up their designs, they are essentially blind as to what physical issues they are creating with their design plan," said Reed. "Calypso will allow design teams to make informed critical design decisions very early in the design cycle."
Getting a jump on physical issues with Calypso has allowed beta customers to create designs 30 percent smaller and 15 percent faster-and 10 percent less costly to make-than designs that did not leverage the technology, Reed said.
Models on tap
Beta customers include Toshiba, Fujitsu and Ricoh.
In keeping with Monterey's approach, Calypso will be used in a successive-refinement methodology. Designers are expected to use Calypso pre-RTL to create models of various blocks and functions in a design. The models will be specified in Verilog and will provide timing, power and area requirements.
The tool then finds an optimum layout and lets a design architect find an optimum mix of timing, area and power.
Because Calypso merges the estimation capabilities of IC Wizard with the design capabilities of Sonar, Reed said the tool allows for hierarchical timing and power.
Users thus can optimize the timing of a path that spans multiple blocks without going into each block and optimizing each subpath within the design's timing path.
If a power rail is widened at the chip level, Calypso can instantly and incrementally measure the effect on IR drop inside all of the blocks, Reed said.
When a timing change is made, users are told immediately how the timing change affects inter- and intrablock IR drop, and vice versa, he said.
Once a satisfactory prototype has been completed, a design group can generate RTL blocks that make up the layout and then run the blocks through synthesis.
Sonar technology then takes over. Users can do design planning with Calypso, optimizing the gates in the design. The tool generates an optimized placement gate-level netlist in industry standard formats, ready for a physical design tool.
Calypso starts at $225,000 for a one-year subscription.
By Michael Santarini, EE Times
Jun 2, 2003 (8:06 AM)
URL: **broken link removed**
San Mateo, Calif. - Monterey Design Systems will preview its Calypso silicon virtual prototyping system at the Design Automation Conference this week.
Monterey created the tool by merging its Sonar physical-synthesis tool with the IC Wizard design planner gained when it acquired Aristo Technology Inc. Built atop a hierarchical database, the tool combines hierarchical design planning, physical synthesis and physical prototyping. It replaces the individual IC Wizard and Sonar tools.
Dave Reed, vice president of marketing at Monterey (Sunnyvale, Calif.), said Calypso is the first tool to take designers from pre-RTL physical prototyping through to placement of optimized gates.
"When design architects are drawing up their designs, they are essentially blind as to what physical issues they are creating with their design plan," said Reed. "Calypso will allow design teams to make informed critical design decisions very early in the design cycle."
Getting a jump on physical issues with Calypso has allowed beta customers to create designs 30 percent smaller and 15 percent faster-and 10 percent less costly to make-than designs that did not leverage the technology, Reed said.
Models on tap
Beta customers include Toshiba, Fujitsu and Ricoh.
In keeping with Monterey's approach, Calypso will be used in a successive-refinement methodology. Designers are expected to use Calypso pre-RTL to create models of various blocks and functions in a design. The models will be specified in Verilog and will provide timing, power and area requirements.
The tool then finds an optimum layout and lets a design architect find an optimum mix of timing, area and power.
Because Calypso merges the estimation capabilities of IC Wizard with the design capabilities of Sonar, Reed said the tool allows for hierarchical timing and power.
Users thus can optimize the timing of a path that spans multiple blocks without going into each block and optimizing each subpath within the design's timing path.
If a power rail is widened at the chip level, Calypso can instantly and incrementally measure the effect on IR drop inside all of the blocks, Reed said.
When a timing change is made, users are told immediately how the timing change affects inter- and intrablock IR drop, and vice versa, he said.
Once a satisfactory prototype has been completed, a design group can generate RTL blocks that make up the layout and then run the blocks through synthesis.
Sonar technology then takes over. Users can do design planning with Calypso, optimizing the gates in the design. The tool generates an optimized placement gate-level netlist in industry standard formats, ready for a physical design tool.
Calypso starts at $225,000 for a one-year subscription.