Proteus Simulation Error: "SCS bits have been set. This feature is not modeled"

[chandlerbing65nm]

Greetings!

I have a problem in simulating interrupt/timer0 code in Proteus using PIC18F4520. It says,

"SCS bits have been set. This feature is not modeled. The model continues to clock itself as before".

Here's the main code:

#include <xc.h>
#include <pic18f4520.h>
#include "osciconbits.h"
#include "stdint.h"
#include "stdbool.h"

uint8_t count = 0;
uint8_t button = 0;
bool button_press = false;


void __interrupt() high_isr(void)
{
     INTCONbits.GIEH = 0;
    
     if (INTCONbits.TMR0IF)
     {
         count++;
         if (button_press)
         {
             button++;
         }
     }
    
     INTCONbits.GIEH = 1;
}


void __interrupt(low_priority) low_isr(void)
{
    INTCONbits.GIEH = 0;
   
   
    INTCONbits.GIEH = 1;
}


void main(void) {
   
   
    OSCCONbits.IRCF =  0x07; //8MHz internal clock
    OSCCONbits.SCS =  0x03; //choose internal clock
           
    while(OSCCONbits.IOFS!=1);
   
   
    TRISBbits.RB6 = 0;
    TRISBbits.RB7 = 0;
   
    TRISBbits.RB1 = 1;
   
    LATBbits.LB6 = 0;
    LATBbits.LB7 = 0;
   
    T0CONbits.TMR0ON = 0;
    T0CONbits.T08BIT = 1;
    T0CONbits.T0CS = 0;
    T0CONbits.PSA = 0;
    T0CONbits.T0PS = 2; //1:8 prescaler
          
   
    RCONbits.IPEN = 1;
   
    INTCONbits.TMR0IE = 1;
    INTCON2bits.TMR0IP = 1;
   
   
    INTCONbits.GIEH = 1;
    INTCONbits.GIEL = 1;
   
    T0CONbits.TMR0ON = 1;
   
    while(1)
    {
        if (count >= 200)
        {
           
                LATBbits.LB7 = ~LATBbits.LB7;
                count = 0;
        }
       
        if (!button_press)
        {
            if (PORTBbits.RB1)
            {
                button_press = true;
            }
        }
       
        if (button_press)
        {
            if (button >= 40)
            {
                if (PORTBbits.RB1)
                {
                    LATBbits.LB6 = ~LATBbits.LB6;
                    button_press = false;
                    button = 0;
                }
                else
                {
                    button_press = false;
                    button = 0;
                }
            }
        }
    }
   
}

and here's the configuration bits:

#ifndef OSCICONBITS_H
#define OSCICONBITS_H

#include <xc.h> // include processor files - each processor file is guarded.
#define _XTAL_FREQ 8000000
// PIC18F4520 Configuration Bit Settings

// 'C' source line config statements

// CONFIG1H
#pragma config OSC = INTIO67    // Oscillator Selection bits (Internal oscillator block, port function on RA6 and RA7)
#pragma config FCMEN = OFF      // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
#pragma config IESO = OFF       // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)

// CONFIG2L
#pragma config PWRT = OFF       // Power-up Timer Enable bit (PWRT disabled)
#pragma config BOREN = OFF      // Brown-out Reset Enable bits (Brown-out Reset disabled in hardware and software)
#pragma config BORV = 3         // Brown Out Reset Voltage bits (Minimum setting)

// CONFIG2H
#pragma config WDT = OFF        // Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))
#pragma config WDTPS = 32768    // Watchdog Timer Postscale Select bits (1:32768)

// CONFIG3H
#pragma config CCP2MX = PORTC   // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
#pragma config PBADEN = OFF     // PORTB A/D Enable bit (PORTB<4:0> pins are configured as digital I/O on Reset)
#pragma config LPT1OSC = OFF    // Low-Power Timer1 Oscillator Enable bit (Timer1 configured for higher power operation)
#pragma config MCLRE = ON       // MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled)

// CONFIG4L
#pragma config STVREN = ON      // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
#pragma config LVP = ON         // Single-Supply ICSP Enable bit (Single-Supply ICSP enabled)
#pragma config XINST = OFF      // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))

// CONFIG5L
#pragma config CP0 = OFF        // Code Protection bit (Block 0 (000800-001FFFh) not code-protected)
#pragma config CP1 = OFF        // Code Protection bit (Block 1 (002000-003FFFh) not code-protected)
#pragma config CP2 = OFF        // Code Protection bit (Block 2 (004000-005FFFh) not code-protected)
#pragma config CP3 = OFF        // Code Protection bit (Block 3 (006000-007FFFh) not code-protected)

// CONFIG5H
#pragma config CPB = OFF        // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected)
#pragma config CPD = OFF        // Data EEPROM Code Protection bit (Data EEPROM not code-protected)

// CONFIG6L
#pragma config WRT0 = OFF       // Write Protection bit (Block 0 (000800-001FFFh) not write-protected)
#pragma config WRT1 = OFF       // Write Protection bit (Block 1 (002000-003FFFh) not write-protected)
#pragma config WRT2 = OFF       // Write Protection bit (Block 2 (004000-005FFFh) not write-protected)
#pragma config WRT3 = OFF       // Write Protection bit (Block 3 (006000-007FFFh) not write-protected)

// CONFIG6H
#pragma config WRTC = OFF       // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)
#pragma config WRTB = OFF       // Boot Block Write Protection bit (Boot block (000000-0007FFh) not write-protected)
#pragma config WRTD = OFF       // Data EEPROM Write Protection bit (Data EEPROM not write-protected)

// CONFIG7L
#pragma config EBTR0 = OFF      // Table Read Protection bit (Block 0 (000800-001FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR1 = OFF      // Table Read Protection bit (Block 1 (002000-003FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR2 = OFF      // Table Read Protection bit (Block 2 (004000-005FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR3 = OFF      // Table Read Protection bit (Block 3 (006000-007FFFh) not protected from table reads executed in other blocks)

// CONFIG7H
#pragma config EBTRB = OFF      // Boot Block Table Read Protection bit (Boot block (000000-0007FFh) not protected from table reads executed in other blocks)

// #pragma config statements should precede project file includes.
// Use project enums instead of #define for ON and OFF.


#endif    /* XC_HEADER_TEMPLATE_H */

And here's the circuit configuration:

The functionality of the code is to blink the RB7 periodically and turn on the RB6 if the push-button is pressed. Debouncing is added to the code for the button pressing. But the simulation fails and no LED's are turning on, this is the error/warning message I'm getting:

Hope someone can answer this. Thanks!

Regards,
Chandler

 

[FvM]

What do you want to achieve with enabling GIEH in interrupt?

 

[chandlerbing65nm]

What do you want to achieve with enabling GIEH in interrupt?

I enabled GIEH = 1 to use the

void __interrupt() high_isr(void)

and GIEL = 1 for

void __interrupt(low priority) low_isr()

 

[KlausST]

Hi,

Your pushbutton circuit is completely wrong. It short circuits the supply.

Klaus

 

[chandlerbing65nm]

Hi,

Your pushbutton circuit is completely wrong. It short circuits the supply.

Klaus

Oh did not notice that. Thanks. But after changing the connection of the push-button, the LED's are still not turning on. Not even RB7 that should blink periodically.

 

[FvM]

Your code is enabling GIEH in both interrupt functions, which definitely causes recursive interrupt triggering.

 

[chandlerbing65nm]

Your code is enabling GIEH in both interrupt functions, which definitely causes recursive interrupt triggering.

I have tried removing the GIEH = 1 in interrupt function but the result error is still the same.