ultegra
Newbie level 1
Hello! First, I apologize for my bad English.
I am designed a device in ISIS as shown in the image below
I have assigned to it a package
Then, when I select the device in another project, I click in its properties
I uncheck "Exclude from PCB layout" and I select the package
Finally, I choose "NETLIST to ARES" option and the device does not appear in ARES
Could anyone tell me what am I doing wrong? Thank you.
I am designed a device in ISIS as shown in the image below
I have assigned to it a package
Then, when I select the device in another project, I click in its properties
I uncheck "Exclude from PCB layout" and I select the package
Finally, I choose "NETLIST to ARES" option and the device does not appear in ARES
Could anyone tell me what am I doing wrong? Thank you.