Protection of VHDL and/or AHDL codes

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sir-yuri

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Can I add some instruction or option to define specific FPGA (CPLD)device in my project. My Customer is given 'edif' or 'tdo' files for further sinthesis. I do not want him to implement another device except specified one for compilation. How to protect my design?
8O
 

I donot know, but I have a idea, I remember that Xilinx FPGA can access its JTAG logic from internal logic, if you can do that, you can access the special JTAG ID of the FPGA, it indicates what type of part it is. so you can lock it!! just my thoughts, hope you can get it
 

I am not very sure if you can access JTAG logic from inside, check it yourself. if it is good, let me know, maybe I will do it next time
 

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