[SOLVED] proplem in verilog-a code

i design sar adc and there is a proplem in sar logic code
the command @(initial_step) saw the first command only (ex. see counter=0) and the other statement repeated in code and i want to make them initial only

this is the code

// VerilogA for try, try, veriloga

`include "constants.vams"
`include "disciplines.vams"
module sar(comp,reset,clk,s1,s2,sp1,sp2,sp3,sn1,sn2,sn3);
input comp,reset,clk;
output s1,s2,sp1,sp2,sp3,sn1,sn2,sn3;
electrical comp,reset,clk,s1,s2,sp1,sp2,sp3,sn1,sn2,sn3;
parameter real Vlow = -1.2 ;
parameter real Vhigh = 1.2 ;
integer counter;
analog
begin
@(initial_step)
counter=0;
//V(s1)<+Vhigh; V(s2)<+Vhigh; V(sp1)<+Vhigh; V(sp2)<+Vhigh; V(sp3)<+Vhigh; V(sn1)<+Vhigh; V(sn2)<+Vhigh; V(sn3)<+Vhigh;
@(cross(V(clk)-1,+1))
counter=counter+1;
if (counter==1) begin
V(s1)<+Vlow; V(s2)<+Vlow;
end
if (counter==2) begin
if (V(comp)>Vhigh/2) begin
V(sp1)<+Vlow;
end
else if (V(comp)<Vhigh/2) begin
V(sn1)<+Vlow;
end
end
if (counter==3) begin
if (V(comp)>Vhigh/2) begin
V(sp2)<+Vlow;
end else if (V(comp)<Vhigh/2) begin
V(sn2)<+Vlow;
end
end
if (counter==4) begin
if (V(comp)>Vhigh/2) begin
V(sp3)<+Vlow;
end else if (V(comp)<Vhigh/2) begin
V(sn3)<+Vlow;
end
end
if (counter==5) begin
counter=0;
end
end
endmodule