Formal tools called property checkers can mathematically prove that, given an RTL design and some assumptions about the relationships of the input signals, an assertion will always hold true. If a counter example is found, the formal tool will provide details on the sequence of events that leads to the assertion violation.
If this is true, do we still need to carry out simulation with all those assertions? Can you give me example of an actual property (also known as assertion prover) checker as I think this funtionality is not present in ModelSim and Formal verification tools are quite expensive.
I must say, I am quite intrigued by these formal verification tools! Does Static Timing Analyzer form part of Formal verification tools as it also uses mathematics to verify that the design has no timing violations and does not need input stimulus or simulation to do this.