Properly simulating CBCPW in Momentum-high frequencies >100GHz

Hi there:

I am trying to figure out which is the best way of simulating a CBCPW (conductor backed CPW) in Mometum ADS 2009. I am using a GaAs substrate (E_r=12.9, loss tg=0.006 and h=100um) as dielectric. I am trying to simulate high frequency structures (up to 300GHz).

I have tried simulating various ways:

1. defining slot structure and simulating the structure using 4 coplanar ports (the ones on the same side being associated to one other and with reversed polarity-just as indicated by ADS documantation).

2. defining strip structure, with 2 top GND planes and the central conducting line in between. As for the ports in this case I have tried both: single for the central conducting line and ground reference for the ports connected at the edges of the two top GND planes, as well as internal for the central conducting line and ground refference for the two top GND planes, when thses ports are moved a bit inside the GND plane - done according to "Methods of Simulating Structures on Electrically Thick Substrates" help file on edocs agilent webpage.

-for both methods the bottom GND is considered infinite

Now all simulation methods give distinct results. The better one is the one which is slot based model, but the problemwith that is that it does not account for losses in the conductor and it considers the top GND planes infinite. The strip based models give worse results, with increased radiation.

I know that when using CBCPW it is recommended using vias to connect top with bottom GND, this is the next step, but previously I would like to know which of the method is closer to a practical measurement? If anyone has any experinece with properly simulating CBCPW structures in Momentum I would certainly need his feedback on the problem.

Thanks a lot!

As you said yourself, since slot mode does not account for conductor losses and and top ground strips are considered infinite, it will give a very optimistic result.
Your best shot is strip mode.

Geoffrey_85 said:

single for the central conducting line and ground reference for the ports connected at the edges of the two top GND planes, as well as internal for the central conducting line and ground refference for the two top GND planes, when thses ports are moved a bit inside the GND plane - done according to "Methods of Simulating Structures on Electrically Thick Substrates" help file on edocs agilent webpage.

Click to expand...

You better to use single ports for center conductors, because calibration procedure that is used for single ports usually gives more realistic results.
You don't have to move ground ports inside the GND plane. This way Momentum will not take coupling between ports into consideration which has a large effect at these frequencies.

Don't be surprised when you measure your circuit and find out that there is a big difference between simulated and measured insertion loss. The main reason is the discontinuity which again has a large effect at these high frequencies.

Hello:

Thaks for giving me your feedback. It's just what I was afraid of. I knew it would be very possible that slot based simulation could yield more optimistic results than it would rather happen in practice.

If yoy say using single ports on strip based model is best choice to follow, what should be the minimum lateral extent of the top GND planes? Is there any practical rule of thumb? From what I know they should be at least W+2G (W=width o central line;G=width of slot). Correct me if I am wrong? Do you have any practical confirmation on this size limitation? Sould it be >W+2G or should it be a couple of times more (n*(W+2G))? n=???

In order to avoid unwanted higher order modes, like parallel plate modes, the width of the top GND planes should be as small as possible, or if circuit design requirements prevent this, one should use vias all along the CBCPW structure in order to short circuit these unwanted modes. As for the slot modes, they should be suppressed and no airbridge should be necessary (only at discontinuities) if and only if the top surface is fully metalized, meaning that the dielectric does not extend beyond the width of the top GND planes.

Could you please give me your feedback on the statements I presented?

Thanks a lot for your help!
Kind regards,

George.

Hamid.Kiumarsi said:

As you said yourself, since slot mode does not account for conductor losses and and top ground strips are considered infinite, it will give a very optimistic result.
Your best shot is strip mode.




You better to use single ports for center conductors, because calibration procedure that is used for single ports usually gives more realistic results.
You don't have to move ground ports inside the GND plane. This way Momentum will not take coupling between ports into consideration which has a large effect at these frequencies.

Don't be surprised when you measure your circuit and find out that there is a big difference between simulated and measured insertion loss. The main reason is the discontinuity which again has a large effect at these high frequencies.

Click to expand...

Geoffrey_85 said:

If yoy say using single ports on strip based model is best choice to follow, what should be the minimum lateral extent of the top GND planes? Is there any practical rule of thumb? From what I know they should be at least W+2G (W=width o central line;G=width of slot). Correct me if I am wrong? Do you have any practical confirmation on this size limitation? Sould it be >W+2G or should it be a couple of times more (n*(W+2G))? n=???

Click to expand...

Normally W+2G is enough but you can extend top ground more than this value.
The major drawback of large top grounds is their size as expected. If size is not your concern, I would choose ground planes large if I were you, because this way you are partially shielding your center line from unwanted couplings and noise.
The right way around to know the effect is to simulate different topologies. If I remember correctly, I think I have checked the effect of top ground plane size, and there was no obvious difference between results. (but I had used lots of vias to connect top grounds to the bottom ground).

Geoffrey_85 said:

In order to avoid unwanted higher order modes, like parallel plate modes, the width of the top GND planes should be as small as possible, or if circuit design requirements prevent this, one should use vias all along the CBCPW structure in order to short circuit these unwanted modes

Click to expand...

Yes, you should use vias and I think it's a must at W band. This way the quality of your ground will be improved.

Geoffrey_85 said:

As for the slot modes, they should be suppressed and no airbridge should be necessary (only at discontinuities) if and only if the top surface is fully metalized, meaning that the dielectric does not extend beyond the width of the top GND planes.

Click to expand...

As far as I know, if you have discontinuity (just to be sure that we are on the same page, by discontinuity here I mean something like 90 degrees cross) using airbridge is a good practice and I don't understand what it has to do with top surface being fully metalized. But we can say that using vias also obviates the need for airbridges in here.

Hello again:

Thank you for being so prompt and giving me your feednack on the problem. We were on the same page with discontinuities, in fact where I have T junctions I use airbridges (even though you say that if placing enogh vias along the CPW top planes you can avoid the use of the airbridges...I will investigate that). I will also make some simulations for different top GHD widths to check the behaviour. There is only one doubt: according to "On the use of vias in conductor-backed coplanar circuits" by William H. Haydl, IEEE, if the width of the top GND is smaller higher order modes (parallel plate modes) are pushed into higher frequency bands, according to formula:

f_m,n=c/2*sqrt(eps_r)*sqrt[(m/Wg)**2+(n/Lg)**2], where:


f_m,n-resonant frequency
c-velocity of light
eps_r-relative dielectric constant
Wg,Lg-width and length of top GND
m,n-higher order modes.

According to this eq, a small Wg can result in f_m,n higher than the operating frequency, yielding mode-free operation. About making the top GND planes wide, what do you mean more precisely by :"this way you are partially shielding your center line from unwanted couplings and noise"??? Do you mean unwanted couplings or noise from other structures around? Having the widths large you isolate the center conducting line from other devices that may reside on the same wafer?

Wainting for your feedback when you got a moment! Thank you,

Kind regards,

George.

Hamid.Kiumarsi said:

Normally W+2G is enough but you can extend top ground more than this value.
The major drawback of large top grounds is their size as expected. If size is not your concern, I would choose ground planes large if I were you, because this way you are partially shielding your center line from unwanted couplings and noise.
The right way around to know the effect is to simulate different topologies. If I remember correctly, I think I have checked the effect of top ground plane size, and there was no obvious difference between results. (but I had used lots of vias to connect top grounds to the bottom ground).



Yes, you should use vias and I think it's a must at W band. This way the quality of your ground will be improved.



As far as I know, if you have discontinuity (just to be sure that we are on the same page, by discontinuity here I mean something like 90 degrees cross) using airbridge is a good practice and I don't understand what it has to do with top surface being fully metalized. But we can say that using vias also obviates the need for airbridges in here.

Click to expand...

Geoffrey_85 said:

According to this eq, a small Wg can result in f_m,n higher than the operating frequency, yielding mode-free operation. About making the top GND planes wide, what do you mean more precisely by :"this way you are partially shielding your center line from unwanted couplings and noise"??? Do you mean unwanted couplings or noise from other structures around? Having the widths large you isolate the center conducting line from other devices that may reside on the same wafer?

Click to expand...

Yes, I meant couplings or noise from other structure/circuits on the same wafer.
However, this is merely my experience below 30 GHz.
Thanks for mentioning the paper by William H. Haydl, it was very interesting.
Again the best way to know what happens if you increase the width is simulating it in Momentum. If your setup is correct, then your simulated results can be trusted.

As a final note, at these frequencies every small detail can cause a problem. I had simulated and measured transmission lines up to 110 GHz and surprisingly there was a big difference between simulated and measured results.
The main source of the error was discontinuity between GSG pad and transmission line. But since you are using CPW lines, I think this problem will be less pronounced in your case.