Proper way to increase the effective length of the transistor

[mixed_signals]

Hello All,


We can increase the length of the transistors by two ways:
1- Increasing the channel length of the transistor directly, though PDKs have a max limit for the channel length that we can not get beyond it.
2- Increasing the number of stacked "smaller channel length" transistors to achieve a larger effective length.

Assuming I need an effective length of 120nm --> Should I use a single transistor with a channel length of 120nm or 4 (30nm) stacked transistors in series?

 

[dick_freebird]

You may not need all 4 30nm series devices if your
interest is only Rout and not voltage reliability /
division. Common gate "self cascode" can raise
Rout more than an equal-sum-L especially if bodies
can be separated (like SOI).

If technology is fixed-L like fin types, your choice has
already been made.

 

[mixed_signals]

You may not need all 4 30nm series devices if your
interest is only Rout and not voltage reliability /
division. Common gate "self cascode" can raise
Rout more than an equal-sum-L especially if bodies
can be separated (like SOI).

If technology is fixed-L like fin types, your choice has
already been made.

Thank you!

I know about the cascode however I mean if both implementation choices are available, which one is more recommended to implement the required effective length?

 

[sidun.av]

As @dick_freebird already mentioned, it depends on what you are trying to achieve here...
If you just need a transistor with a certain effective length, it's better to increase the channel length directly since you don't need to care about second order effects such as substrate impact, layout effects and so on.

 

[dick_freebird]

It would be best for OP to make a simulation with all
of the choices represented (L=120n, L=30n So1, So2,
So3, So4) and observe outcomes, to pick between. It
is not at all certain that L alone is, or is the most appropriate
"knob" for a particular bit of circuit. Like, maybe cascode
is better if you only care about Rout, but maybe cascode
headroom required is too high for your gain-stage load
to work across common mode input range. Who knows?
Simulate it like you mean to use it.

Bearing in mind that (especially in "digital" design kits)
analog nuances (like impact ionization "curl" on short
channel devices) and gross effects (like actual junction
reverse conduction during time in breakdown range)
are not at all, or various kinds of poorly, represented by
different compact models. A peek at that (esp. whether
D-B, S-B currents are sane, outside first quadrant and
further out in first quadrant) is always a good idea in
picking up new technology, so you know where the
sidewalk ends and tiger pits start.

 

[mixed_signals]

As @dick_freebird already mentioned, it depends on what you are trying to achieve here...
If you just need a transistor with a certain effective length, it's better to increase the channel length directly since you don't need to care about second order effects such as substrate impact, layout effects and so on.

Thanks for your response.

I heard that to achieve a larger effective length by stacking multiple shorter length devices is better since they are well modelled however larger length devices' models are interpolated but I can't verify this information so that I want people here to confirm or criticize this info based on their experience.

 

[dick_freebird]

Thanks for your response.

I heard that to achieve a larger effective length by stacking multiple shorter length devices is better since they are well modelled however larger length devices' models are interpolated but I can't verify this information so that I want people here to confirm or criticize this info based on their experience.

You might instead think that the short devices are "well" modeled because they are so production-edgy that they need it (and they represent the raw numbers used).

But modelers are given "care-abouts" too, and for digital flows that can be as weak as just timing match to test chip ring osc results, freq and Idd. If you care about analog nuances then find a way to check realism.

 

[mixed_signals]

I observed that stacked transistor version has better mismatch behaviour than a single transistor with same combined length. Does anyone know why is that?

 

[dick_freebird]

I would not rule out bad modeling.

But if lambda MM is varied statistically, it could affect the single
device strongly while the current-setting device in the stacked
structure has no lambda sensitivity (shielded by N above
cascodes and held to low voltage).

You should poke around and draw conclusions about "why?".
We are unable to poke except by proxy, so conclusions are
limited by that at this end.