propagation delay of cmos inverter

[steven23]

for CMOS inverter, if my propagation delay of a gate is given to be 5ns. what should be the maximum operating frequency for correct output logic level.( if i am having a chain of inverters)??

 

[psurya1994]

To be accurate, it depends on the number of inverters you are having. Let us assume you have 'x' inverters.
You know f = 1/T. So the maximum operating frequency = 1/(5ns*n) = (200MHz/n).
So if you have 2 gates, the maximum operating frequency is 200MHz.

Hope you got the point.

 

[steven23]

for 2 inverters, shouldn't it be T= 2*2*5ns? because we are considering both HL and LH transitions in one complete cycle.

 

[steven23]

and what if rise time/fall time is greater than propagation delay of a gate, then what will be the clock period?

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and what if rise time/fall time is greater than propagation delay of a gate, then what will be the clock period?

 

[psurya1994]

I don't think you need to multiply the time delay by two as you have two edges but I'm not sure.

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I don't think you need to multiply the time delay by two as you have two edges but I'm not sure.