propagation delay of cmos inverter

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steven23

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Hi,,I have a query regarding the propagation delay in a gate,propagation delay is generally measured between 50 percent points on the input and output waveforms, why cannot we measure it between 20% or 80% points on the waveforms ? Is there any specific reason for opting 50% points ??
 

50 % is the typical threshold for many logic families. Thus the 50% measurement is giving the actual delay of cascaded logic gates.
 

but shouldn't the output change its logic level after this delay?? suppose output changes from VDD to VDD/2..and what if VDD/2 is not at logic zero.
 

Inverters are not always matched. The HL (High-to-Low) and LH (Low-to-High) delay of an unmatched inverter / gate are not equal. This is why, imo, considering the 50% of input and output values for delay calculations makes the most sense because at those points, we would be having the mean HL and LH delays.
 

I am totally agree with you..i will put it in another way : when output changes from VOH to VOH/2..and what if VOH/2 is not at logic zero( i mean this value falls in invalid transition region)
 

Focus on "threshold voltage" mentioned by FvM.

50% of the value is where the device begins to switch.

If you are decreasing the signal level, the device will begin going LOW after reaching VH/2.

Similarly, if you are increasing the signal level, the device will begin going HIGH after VL/2.

These are both 50% levels. Whether or not they are in a valid logic state at these points is irrelevant. What is relevant is that switching begins at these instances which makes them valid measures for delay calculations.
 
thanks for the reply.it was really helpful..
 

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