Project in progress -random questions

madalin1990 · Oct 31, 2012

Because i have a project in progress and questions seem to pile up i choose to open this thread to use for any present and future questions.

Ok.so here is my question:
How to declare and use a 2 dimension variable?Is this declaration correct:

Code:

wire [2:0] variable [23:0]  ;

ads_ee · Oct 31, 2012

madalin1990 said:
How to declare and use a 2 dimension variable?Is this declaration correct:

Code:

wire [2:0] variable [23:0] ;

Yes it is correct, if you want to declare an array of 24 3-bit wide signals called variable. You can also declare the [23:0] as [0:23].

regards,
-alan

madalin1990 · Oct 31, 2012

So if i want to use this signal called variable to connect to 3 different 24-bits ports i write:

Code:

module module_name U_module_name(
.signal1(variable[0],
.signal2(variable[1],
.signal3(variable[2]
);

Correct?

ads_ee · Oct 31, 2012

madalin1990 said:
So if i want to use this signal called variable to connect to 3 different 24-bits ports i write:

Code:

module module_name U_module_name( .signal1(variable[0], .signal2(variable[1], .signal3(variable[2] );

Correct?

If you want 3 different 24-bit ports then the wire declaration would have to be:

Code:

wire [23:0] variable [0:2];

// which can then be used like:
// Note the differences in this instantiation.
module_name  U_module_name (
  .signal1  (variable[0]),
  .signal2  (variable[1]),
  .signal3  (variable[2])
);

// Here is the explicit connection of the array using both dimensions:
module_name  U_module_name (
  .signal1  (variable[0][23:0]),
  .signal2  (variable[1][23:0]),
  .signal3  (variable[2][23:0])
);

regards

madalin1990 · Nov 1, 2012

tnx.this clear it out for me

madalin1990 · Nov 1, 2012

Ok.another question.I want to define a mux with a parametrized size of input and output.I wrote this code but it seems to be a problem with the default case:

Code:

module MUX3TO1(IN0,IN1,IN2,IN3,SEL,OUT);
  parameter width = 5;
  
  input [width-1:0] IN0,IN1,IN2,IN3;
  input [1:0] SEL;
  output reg [width-1:0] OUT;  
  
  always @(SEL or IN0 or IN1 or IN2 or IN3)
       case( SEL )
 2'b00:OUT <= IN0;
 2'b01:OUT <= IN1;
 2'b10:OUT <= IN2;
 2'b11:OUT <= IN3;
 default: OUT<= width'bx;
     endcase
     
 endmodule

Error:near "'b": syntax error, unexpected BASE, expecting ';'

ads_ee · Nov 1, 2012

Code:

 default: OUT<= width'bx;

You can't use a parameter as the bit width constant.

Try this instead.

Code:

 default: OUT <= {width{1'bx}};

Regards

dave_59 · Nov 1, 2012

If you can use SystemVerilog

default: OUT <= 'x;

madalin1990 · Nov 1, 2012

For dave_59:unfortunately I must use only verilog now.But is a good thing to remember for when i'll go system Verilog.
For ads_ee:can you please explain how this line works?I mean i know {} means concatenation,but can't figure exactly how this works.will the bits number of default signal OUT change with width?

ads_ee · Nov 1, 2012

{count{value}}

Means concatenate value count times. So you could easily write 0x5555 as {8{2'b01}} if you wanted.

-alan

madalin1990 · Nov 2, 2012

i understand now.thank you!

madalin1990 · Nov 3, 2012

Code:

parameter HD        = 800;
wire BAR_WIDTH ; 
 assign BAR_WIDTH = HD/8 ;

is this assignation correct?
will BAR_WIDTH have the value 100?

mrflibble · Nov 3, 2012

Yes, if you make that BAR_WIDTH more than it's current 1-bit width. Although if you want some way to derive locally used parameters from the value of other parameters, consider using localparam.

Code:

parameter HD = 800;

localparam BAR_WIDTH = HD/8;

madalin1990 · Nov 3, 2012

touche).

good idea.i will use a local parameter.tnx

madalin1990 · Nov 8, 2012

Browsing the internet i found this code about a RAM with synchronous writing and asynchronous reading:

Code:

module ramA # 

( parameter N = 3,           
  parameter W = 8)            

( input clk,		
  input we,		 
  input [N-1:0] addr,      	 
  input [W-1:0] di,            
  output [W-1:0] dout);        
  
  localparam M = 2**N;	  
  reg [W-1:0] mem [0:M-1];      
                                         
  always @ (posedge clk)        
   if (we)		  //
     mem[addr] <= di;          

  assign dout = mem[addr];     

endmodule

My question is :shouldn't be a "always @(addr)" line code before dout assignation?

mrflibble · Nov 8, 2012

The dout being assigned like that is the "asynchronous reading" bit. ;-)

madalin1990 · Nov 14, 2012

I think i can answer my own question)."assign" is called continuous assignation,and i think this say it all.

madalin1990 · Nov 15, 2012

I must now write some documentation and I was thinking of asking for an advice before begining.So feel free to tell me the steps your following in writing good documentation.

madalin1990 · Nov 20, 2012

I want to write an image pixels value in a memory using readmemh.The problem is that the adress should be bidimensional.I know that for reading the memword at a certain address i write:

Code:

RGB = mem[addr]

But how can i proceed for a bidimensional address?

ads_ee · Nov 20, 2012

madalin1990 said:
I want to write an image pixels value in a memory using readmemh.The problem is that the adress should be bidimensional.I know that for reading the memword at a certain address i write:

Code:

RGB = mem[addr]

But how can i proceed for a bidimensional address?

If your multidemensional address is defined as:

Code Verilog - [expand]
1
2
3
wire [7:0] addr [0:4][0:4];
 
assign RGB = mem[addr[adr_dim1][adr_dim2]];

adr_dim1/2 are the two dimensions you are using to select the pixel.

Code Verilog - [expand]
1 2 3	wire [7:0] addr [0:4][0:4]; assign RGB = mem[addr[adr_dim1][adr_dim2]];

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