programming synthesizer with fpga by SPI

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gaffarnazari@yahoo.com said:
Hi to all. any body can help me for programming synthesizer si4136 with VHDL code?
I need for my final project. any body can help me please send mail to my mail
gaffarnazari@YAHOO.COM
Click to expand... 

Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
 
entity si4136 is
 
port (
  clk    : in std_logic; --100mhz
  rst_n  : in std_logic;
  data   : in std_logic_vector(17 downto 0);
  add    : in std_logic_vector(3 downto 0);
  go     : in std_logic;
  sent   : out std_logic := '0';
  SE_N   : out std_logic := '1';
  SDATA  : out std_logic := '0';
  SCLK   : out std_logic
);
 
end entity si4136;
 
architecture rtl of si4136 is
 
constant COUNT_DELAY : integer range 0 to 7 := 4;
signal wire_send_spi : std_logic_vector(21 downto 0);
signal reg_send_spi : std_logic_vector(21 downto 0) := (others => '0');
signal reg_cnt_spi_clk : integer range 0 to 7:= 0;
signal reg_cnt_data : integer range 0 to 31 := 21;
signal wire_cnt_done , wire_cnt_midle: std_logic;
signal reg_sclk  : std_logic := '0';
type   type_sm_send_spi is (IDLE,RCV_GO,SEND,ENDED);
signal sm_send_spi : type_sm_send_spi;
 
begin
  
  wire_send_spi <= data & add;
  wire_cnt_done <= '1' when reg_cnt_spi_clk = COUNT_DELAY else '0';
  wire_cnt_midle <= '1' when reg_cnt_spi_clk = COUNT_DELAY or reg_cnt_spi_clk = COUNT_DELAY/2 else '0';
  p_seq : process(clk,rst_n) is
  
  begin
  
    if (rst_n = '0') then
      SE_N  <= '1';
      SDATA <='0';
    elsif rising_edge(clk) then
         
      case sm_send_spi is
        
        when IDLE =>
          SE_N  <= '1';
          SDATA <= '0';
          reg_sclk <= '0';
          reg_cnt_data <= 21;
          sent <= '0';
          ------------------
          if (Go ='1') then
            reg_send_spi <= wire_send_spi;
            sm_send_spi <= RCV_GO;
          end if;
        when RCV_GO =>
          SE_N <= '0';
          SDATA <= reg_send_spi(21);
          --------------
          sm_send_spi <= SEND;
        when SEND =>
          if (wire_cnt_done = '1') then
            if (reg_cnt_data > 0) then
              SDATA <= reg_send_spi(reg_cnt_data-1);
            end if;
            if (reg_cnt_data > 0) then
              reg_cnt_data <= reg_cnt_data - 1;
            else
              reg_cnt_data <= 21;
              ---------------
              sm_send_spi <= ENDED;
            end if;
          end if;
          --
          if (wire_cnt_midle = '1') then
            reg_sclk <= not reg_sclk;
          end if;
          --
          if (reg_cnt_spi_clk < COUNT_DELAY) then
            reg_cnt_spi_clk <= reg_cnt_spi_clk + 1;
          else
            reg_cnt_spi_clk <= 0;
          end if;
        when ENDED =>
          SE_N <= '1';
          sent <= '1';
          reg_sclk <= '0';
          sm_send_spi <= IDLE;
          --------------
      end case;
      
    end if;
    
  end process p_seq;
  --
 
Last edited by a moderator:
hi.if I want implementation si4136 to generate 2000 to 2100 MHZ WITH 2 MHZ channel space, how can I implementation with vhdl code this problem?how can I write test bench code for this problem?
 

gaffarnazari@yahoo.com said:
hi.if I want implementation si4136 to generate 2000 to 2100 MHZ WITH 2 MHZ channel space, how can I implementation with vhdl code this problem?how can I write test bench code for this problem?
Click to expand...

gaffarnazari@yahoo.com said:
hi.if I want implementation si4136 to generate 2000 to 2100 MHZ WITH 2 MHZ channel space, how can I implementation with vhdl code this problem?how can I write test bench code for this problem?
Click to expand...

1./ you can read documentation at vendor web page.
https://www.silabs.com/pages/Silabs-Search.aspx?q=si4136

2./you can look at software drivers like linux drivers for device configuration detailes.

3./for testbench you will need to have a model of the device from the vendor, if they give any.
 

I have documetation of si4136 but I want to write vhdl code for implementation for example 2000 t0 2100 with 200 khz channel spacing.to this problem I used fpga spartan3 for send data to si4136, but I have problem in writing code and send data to synthesizer by spi.I dont know how can I set vhdl code for this problem.
thank you for your reply my dear.
 


Code: 
[syntax=vhdl] 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
entity  tb_si4136 is

end entity ;
--------------------------------------------------------------------------------


architecture Bhv of tb_si4136 is
  -----------------------------
  -- Port Signals 
  -----------------------------
signal   clk   : std_logic := '1';
signal   rst_n : std_logic;
signal   data  : std_logic_vector(17 downto 0);
signal   add   : std_logic_vector(3 downto 0);
signal   go    : std_logic;
signal   sent  : std_logic;
signal   SE_N  : std_logic;
signal   SDATA : std_logic;
signal   SCLK  : std_logic;

  
begin  -- architecture Bhv
  
  -----------------------------
  -- component instantiation 
  -----------------------------
  si4136_INST: entity work.si4136
   port map (
      clk   => clk,
      rst_n => rst_n,
      data  => data,
      add   => add,
      go    => go,
      sent  => sent,
      SE_N  => SE_N,
      SDATA => SDATA,
      SCLK  => SCLK);

	clk <= not clk after 5 ns;
	rst_n <= '0','1' after 1 us;
	
  StimuliProcess : process
  begin
    go <= '0';
	wait until rst_n = '1';
	l_i : for i in 1 to 100 loop
	  wait until rising_edge(clk);
	end loop l_i;
	add <= b"0101";
	data <= b"101010101010101010";
	go <= '1';
	--
	wait until rising_edge(clk);
	go <= '0';
	wait until sent = '1';
	report "sent data with address";
	wait;
  end process StimuliProcess;
  
end architecture Bhv;
[/SYNTAX]
 

in the first thank you from yor reply,in SPI protocol we can sen data to method of bit to bit from fpga to si4136,my question is how can I?FOR example if I want generate 2000mhz and after that generate 2020 mhz, how can I write vhdl code respectively to generate 2000 and 2020?
 



ill try to explain how you do it :

1.i attached snipest from si4136 code used by linux device - it is in c,
commands are executed one after another.
each command write different register in the si4136 (via spi).
2. you can do the same thing in your test bench in vhdl by replacing c procedures with vhdl procedures or functions.
3. basically there is only one procedure to implement here "adm8211_rf_write_syn_rfmd2948".
4. so all you to do here is to implement the process i used in a test bench as a vhdl procedure;
then implement the test bench process like it is done in the c program - just copy/paste it.
5. i hope i made my self clear.

Code: 
[syntax=c]
static int adm8211_rf_set_channel(struct ieee80211_hw *dev, unsigned int chan)
{
adm8211_rf_write_syn_rfmd2948(dev, SI4126_MAIN_CONF,SI4126_MAIN_XINDIV2);
adm8211_rf_write_syn_rfmd2948(dev, SI4126_POWERDOWN,
                                               SI4126_POWERDOWN_PDIB |
                                               SI4126_POWERDOWN_PDRB);
adm8211_rf_write_syn_rfmd2948(dev, SI4126_PHASE_DET_GAIN, 0);
adm8211_rf_write_syn_rfmd2948(dev, SI4126_RF2_N_DIV,(chan == 14 ?2110 : (2033 + (chan * 5))));
adm8211_rf_write_syn_rfmd2948(dev, SI4126_IF_N_DIV, 1496);
adm8211_rf_write_syn_rfmd2948(dev, SI4126_RF2_R_DIV, 44);
adm8211_rf_write_syn_rfmd2948(dev, SI4126_IF_R_DIV, 44);
}
[/syntax]
 

Very thanks. my friend I know how I can write vhdl code but I cant write respectively.for example I know Nif or Nrf=... but I dont know how can I write rows of vhdl code?I will try to write code and share here.
 

HI.I simulated the first code but when I generate testbench for si4136:
ENTITY testbenchsi4136 IS
END testbenchsi4136;

ARCHITECTURE behavior OF testbenchsi4136 IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT si4136
PORT(
clk : IN std_logic;
rst_n : IN std_logic;
data : IN std_logic_vector(17 downto 0);
add : IN std_logic_vector(3 downto 0);
go : IN std_logic;
sent : OUT std_logic;
SE_N : OUT std_logic;
SDATA : OUT std_logic;
SCLK : OUT std_logic
);
END COMPONENT;


--Inputs
signal clk : std_logic := '1';
signal rst_n : std_logic := '0';
signal data : std_logic_vector(17 downto 0) := (others => '0');
signal add : std_logic_vector(3 downto 0) := (others => '0');
signal go : std_logic := '0';

--Outputs
signal sent : std_logic;
signal SE_N : std_logic;
signal SDATA : std_logic;
signal SCLK : std_logic;

-- Clock period definitions
constant clk_period : time := 10 ns;
constant SCLK_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: si4136 PORT MAP (
clk => clk,
rst_n => rst_n,
data => data,
add => add,
go => go,
sent => sent,
SE_N => SE_N,
SDATA => SDATA,
SCLK => SCLK
);

-- Clock process definitions
clk_process rocess
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;

SCLK_process rocess
begin
SCLK <= '0';
wait for SCLK_period/2;
SCLK <= '1';
wait for SCLK_period/2;
end process;


-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;

wait for clk_period*10;

-- insert stimulus here

wait;
end process;

END;


this code have this error:
ERROR: The Top module has not been specified. This can happen if no sources have been added to the project,
best regards.
 


The Error Is Very Clear : You did not attached your UUT to the project.
 

HI.I want programming synthsizer si4136 with fpga. but I dont know how can I start?the si4136 has three pin for programmig, sclk and SEN and SDATA. IF I DESCRIBE it operation:
when sclk event and sclk=1 and SEN=0 the sdata IS ACTIVE and with edge up sclk=1 a bit of sdata transfer to internal register of si4136.if I want to programming for example reg1 and reg3 and reg6(when is RF operation) .how should I do?
sclk(cycle time)=40ns(minimum)
SEN(PULSE WIDTH)= 10ns(when SEN=1)

- - - Updated - - -

I delete uut but that has this errore again:
ERROR: The Top module has not been specified. This can happen if no sources have been added to the project,
 

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