Programming Lattice iCE40LP

Hi All,

edaboard user pointed me to Lattice iCE40LP low end FPGA chips as an inexpensive replacement of bigger CPLDs.
Chips looks really interesting to me even though they require 1.2V, 2.5V and eventually 3.3V power supplies.
I decided to give them a try.
The chips includes nonvolatile memory but from the documentation it is not clear how one can program them from the SPI bus.
Setting of the chip behavior thru the SPI is well documented though.
They only say that nonvolatile memory can be programmed using Lattice diamond programmer.

Anyone having experience with Lattice iCE40LP programming using CPU and SPI bus?

Thanks
Dora

I can't tell about the programming but I would like to warn you about the package of these devices. They are very small and they can cause problem with the PCB layout. Make sure that your PCB fab and the assembly manufacturer are ok with the package you choose.

For the programming, you can verify with the iCEstick development board and try for yourself.

Did you look at the following on Lattice's web site? Pages 17-20 seem to do a pretty good job of describing the procedure to program the part as a SPI slave with a uC/uP.

I also proposed using a Actel/Microsemi ProASIC3 nano part, which only requires 1.5V for the core and can have 1.5V, 1.8V, 2.5V, or 3.3V I/O voltages. Not sure if the number of voltage rails on the iCE40LP you quoted is due to two I/O rails too.

The ProASIC3 nano in-system programming requires JTAG ISP, which is only slightly more complicated than SPI programming (assuming you build your own programming interface in the CPU/uC). As I recall the tools can spit out an SVF file which I would imagine there is code available to interpret that.

The nano is also non-volatile so that could be a benefit if there is a start up requirement that is tight.

Hi Gents,

@Tetik
Thanks for the remark.
I have selected 32QFN part with 0.5mm pitch which should be OK.
Now I see they have 0.35mm pitch componenets which indeed we have to keep far from.

@ads-ee
Yes I have study this document and from what I have undestood there are not clean definition about the programming of non-volatile memory.
On the pages you pointed out they define how to load the settings in the volatile chip memory.

We have considered Actel and Microsemi but for the size we need (around 300 FF cells ) Lattice seems to be the bestprice ($1.5 retail in catalog distributors)
iCE40LP384 requires 1.2Vcc for the core, 2.5Vpp for the programming which needs to stay on all the time and 3.3Vio to interface our 3.3V logic

Thanks
Dora

dora said:

We have considered Actel and Microsemi but for the size we need (around 300 FF cells ) Lattice seems to be the bestprice ($1.5 retail in catalog distributors)
iCE40LP384 requires 1.2Vcc for the core, 2.5Vpp for the programming which needs to stay on all the time and 3.3Vio to interface our 3.3V logic

Thanks
Dora

Click to expand...

You should analyze the cost trade off with using an Actel/Microsemi as there will be one less supply rail (unless you already have to use that extra rail for something else) with all of it's associated passives included. Don't know if your application would benefit from the non-volatile nature of the Microsemi parts.

ads-ee said:

You should analyze the cost trade off with using an Actel/Microsemi as there will be one less supply rail (unless you already have to use that extra rail for something else) with all of it's associated passives included. Don't know if your application would benefit from the non-volatile nature of the Microsemi parts.

Click to expand...

yes I would like to use non-volatile fpga as don't want to put external memory.
Startup behaviour is not very critical for this project, but you mean non-vlatile fpgas configure itself faster?

Dora

dora said:

yes I would like to use non-volatile fpga as don't want to put external memory.
Startup behaviour is not very critical for this project, but you mean non-vlatile fpgas configure itself faster?

Dora

Click to expand...

Actel/Microsemi's ProASIC3 nano, uses flash cells for the configuration, so it doesn't configure at startup. Instead it is always configured (power on or off) and stays that way until reprogrammed. So you don't need external memory for the FPGA and you don't need to keep an FPGA image stored constantly in flash somewhere else in the uP/uC memory. You only need to temporarily store an FPGA image when you want to do any kind of field update of the FPGA.

The Lattice part you were looking at is SRAM based so would require a configuration device or the uP/uC to configure it through the SPI interface from where ever the uP/uC stores the FPGA image.

ads-ee said:

Actel/Microsemi's ProASIC3 nano, uses flash cells for the configuration, so it doesn't configure at startup. Instead it is always configured (power on or off) and stays that way until reprogrammed. So you don't need external memory for the FPGA and you don't need to keep an FPGA image stored constantly in flash somewhere else in the uP/uC memory. You only need to temporarily store an FPGA image when you want to do any kind of field update of the FPGA.

The Lattice part you were looking at is SRAM based so would require a configuration device or the uP/uC to configure it through the SPI interface from where ever the uP/uC stores the FPGA image.

Click to expand...

Well Lattice keeps its 'settings' in SRAM but it also includes non-volatile memory and it has ability to 'boot' its SRAM configuration from the non-volatile memory.
So on my original question. Anyone knowing how to program the iCE40LP non-volatile memory without Lattice diamond programmer?

Dora

Have you asked your local Lattice representative's FAE? If they don't know it - try to contact Lattice itself. If you think that's too much trouble - go for another vendor.