Programming FPGA with uC

[nsgil85]

Hi everyone

Does anybody encounter with a project that uC program the FPGA with JTAG interface on powe up (the uC stores the bitstream on its FLASH)

(FPGAs bitstream file is in Mb)

Thanks
Gil

 

[sythe]

Not with JTAG.
Xilinx has app-notes on how to program their FPGA's via the "normal" programming interface.

See :

https://www.xilinx.com/support/documentation/application_notes/xapp583-fpga-configuration.pdf

 

[nsgil85]

Hi,

Let me clearfy this, I inherited a board (SPARTAN-6) that it's designer forgat to fanout the configure flash pinout.
(no access to the balls on the BGA) - so for bybass that issue each time powers up the uC configre that FPGA

 

[FvM]

Surely possible. Altera provided a "Jrunner" code for the same purpose. Besides handling JTAG (almost easy) you need to understand the JTAG configuration load algorithm used by your FPGA. It should be documented somewhere.

 

[nsgil85]

Ok,

It is for Altera's FPGAs, i'm using SPARTAN-6, couldn't find parralel subject on xilinx.
Is there any referance design you can share with?

BTW
I'm familiar with JTAG chain

Thanks
Gli

 

[Tetik]

Read the XAPP058 application note. I think you will find the answer in this document.

 

[matrixofdynamism]

Why limit only to JTAG?

Alera devices (and Xilinx would be similar) have "passive configuration" capability in which an external device shall configure the FPGA. On development boards this often ends up being a MAX II or MAX V CPLD. Read about passive configuration. A microcontroller could also be used here, it shall just read data from external configuration memory and write to the FPGA.

 

[FvM]

Why limit only to JTAG?

It's said in post #3.