Programming FPGA thorough UART port ?

[doost4]

Hello everybody,

I have a Parallella board with Xilinx Zynq 70Z10 FPGA. Unfortunately, this board doesn't contain a JTAG port. The JTAG port is accessible only by connecting an external expansion board to it. Since this daughter-board connects to exclusive Parallella port named PowerPec, it is not possible to extract the JTAG pins. The question is, is there anyway to program the FPGA not using the JTAG port? For example UART?

Thanks

 

[FvM]

If programming refers to loading a FPGA configuration on-the-fly, it's most likely not possible. Re-programming a connected configuration flash through UART or e.g. Ethernet can work with the help of a boot loader configuration residing in the a sector of the configuration flash, or utilizing the embedded processor.

Nevertheless, programming the boot loader configuration to the flash or performing hardware debugging might require direct JTAG access.

 

[hobbyckts]

FPGA programming through UART port is not possible. It can be done through JTAG only

 

[wtr]

I'm with #2.

You can program a remote device through the fpga. Provided the fpga device initially has - uart module & configuration loader. This way whenever you power cycle the device you have a new fpga image on it...Just for heavens sake don't load an fpga image into flash that doesn't have loader & uart. Then you're royally screwed.

Having done a stint in the space industry I experienced an instances where you couldn't access the jtag to program certain fpgas, however we had a single access CAN bus fpga, which could be used to configure the various fpga's down stream. One guy reconfigured the can bus routing fpga (with a bit file that didn't have loader & can comm bus). We had to take the entire satellite apart so we could access the jtag port & FIX it.

Regardless of what #3 says it can be done. You just need to make sure you have some quality control to ensure you don't remove key parts to the bit file.

 

[sherif123]

wesleytaylor, when you said "(with a bit file that didn't have loader & can comm bus)", did you mean that the hdl code of the FPGA has a certain custom block that can access the flash memory of the FPGA??
I once wrote my own custom HDL code to access the flash of one Altera FPGA to save some data (I did not change the FPGA file)

 

[ads-ee]

wesleytaylor, when you said "(with a bit file that didn't have loader & can comm bus)", did you mean that the hdl code of the FPGA has a certain custom block that can access the flash memory of the FPGA??
I once wrote my own custom HDL code to access the flash of one Altera FPGA to save some data (I did not change the FPGA file)

Yes that is what they meant. The best option for a situation where you can brick a unit by overwriting the "boot-loader" FPGA image is to have two images in the flash, one image is in a protected area of the flash that can't be written by any other means than opening the box up. That image contains the minimum necessary functionality to bring up the FPGA in a mode where it can access flash to write any new images sent to it over whatever interface is coded into it (e.g. UART). This FPGA image should be well tested, i.e. only have the absolute minimum required logic don't add stuff just because it might be useful (that just means more exhaustive testing).

The FPGA loads the power on boot image (from the write protected section of flash) and allows something like a processor to write a operational image or command the FPGA to reconfigure with an operational image from flash.

In Xilinx land this is referred to as fallback configuration.

 

[doost4]

Yes that is what they meant. The best option for a situation where you can brick a unit by overwriting the "boot-loader" FPGA image is to have two images in the flash, one image is in a protected area of the flash that can't be written by any other means than opening the box up. That image contains the minimum necessary functionality to bring up the FPGA in a mode where it can access flash to write any new images sent to it over whatever interface is coded into it (e.g. UART). This FPGA image should be well tested, i.e. only have the absolute minimum required logic don't add stuff just because it might be useful (that just means more exhaustive testing).

The FPGA loads the power on boot image (from the write protected section of flash) and allows something like a processor to write a operational image or command the FPGA to reconfigure with an operational image from flash.

In Xilinx land this is referred to as fallback configuration.

Dear ads-ee, thanks for your explanation. I've read the "MultiBoot and Fallback with SPI Flash in UltraScale FPGAs" provided by Xilinx. As I understood, this Fallback Configuration is also possible by sending some commands to FPGA from the hos computer and the only way to do that is through the JTAG port.
As hobbyckts mentioned in #3 before, it seems that programming the FPGA without the JTAG port is not possible.

 

[vGoodtimes]

Hello everybody,

I have a Parallella board with Xilinx Zynq 70Z10 FPGA. Unfortunately, this board doesn't contain a JTAG port. The JTAG port is accessible only by connecting an external expansion board to it. Since this daughter-board connects to exclusive Parallella port named PowerPec, it is not possible to extract the JTAG pins. The question is, is there anyway to program the FPGA not using the JTAG port? For example UART?

Thanks

From the forums of the manufacturer, it appears you place the bit file on the SD card. It appears something programs the FPGA. It appears you can also program the FPGA from the linux environment on the other processor. This means you can also program the FPGA using ethernet -- perhaps by having the bit file loaded over nfs or etc...