thoughtmaze
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Hi guys noob here, first post. I need to design a program counter to satisfy the following schematic.
and here is my code so far. Now I'm pretty sure this is wrong. But I don't even know how to test this yet using QuartusII, hoping my TA will explain it this Monday. Would someone with more experience take a look and help me figure this out, in particular I am sure I implemented the inc (increment) condition wrong, that is, if inc is high then I should start the count from the output.
any help would be greatly appreciated, thanks in advanced.
and here is my code so far. Now I'm pretty sure this is wrong. But I don't even know how to test this yet using QuartusII, hoping my TA will explain it this Monday. Would someone with more experience take a look and help me figure this out, in particular I am sure I implemented the inc (increment) condition wrong, that is, if inc is high then I should start the count from the output.
Code:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY pc IS
PORT(
clr : IN STD_LOGIC;
clk : IN STD_LOGIC;
ld : IN STD_LOGIC;
inc : IN STD_LOGIC;
d : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
q : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0));
END pc;
ARCHITECTURE description OF pc IS
-- you fill in what goes here!!!
SIGNAL Count:STD_LOGIC_VECTOR (31 DOWNTO 0) ;
BEGIN
PROCESS (clk,clr,ld,inc)
BEGIN
IF clr='0' THEN
Count<="00000000000000000000000000000000";
ELSIF inc='1' THEN
Count<=q;
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld='1' THEN
Count<=Count+4;
ELSE
Count<=Count;
END IF;
END IF;
END PROCESS;
q<=Count;
END description;any help would be greatly appreciated, thanks in advanced.