Program counter (A, B) question?

[dd2001]

Design a 1.9G PLL for GSM, there two program counter, A and B, how to implement them?

Whicn one I should chose from following circuits

1. Simply use verilog to coding and synthesize
2. Use CML circuit?
3. Use TSP circuit?

Thanks

 

[kingsr]

1. Simply use verilog to coding and synthesize


Control A and B register,

Frequency out=[64*(A+B)*Frequency reference

 

[computer_terminator]

Control A and B register,

Frequency out=[64*(A+B)]*Frequency reference

The Frequency out= [Pre *A +B] * Frequency reference
Pre is the prescaler count.

 

[dd2001]

thanks.


Should design prescaler by hand, both schematics and layout? Since it operates around 4Ghz.

 

[computer_terminator]

Yes, you have to design prescaler by hand for operating at 4GHz
You may need use CML flip-flop for your prescaler.

 

[dd2001]

Where can I get a sample code for program counter A and B, also accumulator in verilog or VHDL?


Thanks

 

[computer_terminator]

You can coding it easily, if you know how it work.
They are just 2 programmable counters.
You can find the programmable counter code on the verilog text book.

 

[dd2001]

You can coding it easily, if you know how it work.
They are just 2 programmable counters.
You can find the programmable counter code on the verilog text book.

I am not sure those A, B counter coded in verilog realy works? Someone suggests that to design them by hand and layout by hand, also use diffrencial flip-flops, reduce switch noise. Is there anyone knows what about conmmercial version implementation, do they use verilog to coding A, B stuff.

Also, more on this, do they code accumulator in verilog also?

 

[computer_terminator]

I think you want to design a delta-sigma/ PLL, right?
U can use HDL to design A,B counter as well as accumulator.
If you are good at logic design, you also can design them by hand.