process statement in vhdl confusion

FvM · May 27, 2015

Do you hear at all?

Timing statements, e.g. wait with timeout are not synthesizeable. Please review post #17.

p11 · May 27, 2015

are u atall getting my point . the thing which u said , thats wat i have said in my above post . so wat to do if i want to assign a signal with two different values in a process without a sensitivity list . shouls io give a delay (using a counter ) after each signal assignment .

TrickyDicky · May 27, 2015

p11 said:
is process statement without sensitivity list synthesizable? if no then fine . but if yes then then how ??

No.
Did you find a text book yet?

- - - Updated - - -

p11 said:
are u atall getting my point . the thing which u said , thats wat i have said in my above post . so wat to do if i want to assign a signal with two different values in a process without a sensitivity list . shouls io give a delay (using a counter ) after each signal assignment .

You should read a text book and stop asking the same questions over and over and over again on forums. Perhaps reading the replies you're given would also help?

Did you find a text book yet?

p11 · May 27, 2015

yes after reading the tutorial i have got to know that signal assignment is done only at the end of the process statement .

Code:

begin
process

begin 


a<='1';
a<='0';

end process;

so here a is nly assigned with '0' value .

again somewhere i have read that signal assignment is possible wnhen it encounters a wait statement .

Code:

begin
process

begin 


a<='1';

wait for 10 ns;
a<='0';

wait for 10 ns;

end process;

so here a will be assigned with '1' first and then '0'. since after both signal assignments it is encountering a wait statement .

now we know that wait is not synthesizable, so for synthesis , if i need to assign signal a with '1' and then with '0' what to do ? here i cant use wait as wait is not synthesizable. so then wha to do...

i hope now i have made my problem clear , now plz give a solution .

vGoodtimes · May 27, 2015

are u atall getting my point . the thing which u said , thats wat i have said in my above post . so wat to do if i want to assign a signal with two different values in a process without a sensitivity list . shouls io give a delay (using a counter ) after each signal assignment .

You seem very insistent on this "no sensitivity list" part. If you want to synthesize the design and use it on an FPGA, you should check to see what restrictions your tool vendor has. The "after" delays will be removed. I seem to remember processes would synthesize as long as there was exactly one "wait until" or "wait on" statement that was equivalent to the rising edge of a clock or the sensitivity list respectively. There may have also been a restriction that the "wait" line be the first line of the process. In such a case, there is no advantage over the well established method.

I get the feeling this is all related to that LCD interfacing problem you posted. To do that process, you would have something like:

Code:

fsm_proc : process (clk) is
begin
  if rising_edge(clk) = '1' then
    cnt <= cnt + 1; -- default logic, if nothing else wants to change cnt, cnt will increment.
    -- cnt will not increment on this line. The intent to change cnt will be noted.
    case (state) is
    when INIT_WAIT_100MS =>
      if cnt >= SOME_VALUE then -- you can also use =, sometimes = will synthesize better, sometimes >= will.
        state <= SET_1; -- change to next state
        cnt <= 0; -- this overrides the "cnt <= cnt + 1" line.
        lcd(3 downto 0) <= "0011"; -- setting the value on the transition to the next state will mean the value is set 
        -- upon entering the state, not 1 cycle after entering the state.  This is unimportant for this design*.
      end if;
      when SET_1 =>
        -- very similar code here. 
      -- similar code for each step of the design. **
    end case;
    if rst = '1' then -- placing the reset at the end is more common in FPGA designs***
      -- where not all signals are reset.
      lcd <= (others => '0');
      cnt <= 0;
      -- other signals that need to be reset 
    end if;
  end if;
end process; -- and here is where the actual updates will occur, at the end of the process
-- and after all triggered processes have been evaluated.

You'll need to look up enumerated types, and cnt should be a natural range 0 to N, where N is the max value for the counter. you can also make cnt be unsigned.

* This is a key point to remember in normal clocked processes. It can be easy to add register stages by accident.

** I'm not going to write the entire process out. It will end up being fairly long, though the logic should be fairly simple after synthesis.

*** FPGA manufacturers often suggest only using resets when logically needed.

shaiko · May 27, 2015

p11,

so what to do??

You have to design a synchronous logic circuit that does the same thing.

assuming a 100Mhz system clock

Code:

process ( clock_100mhz , reset ) is 
begin
   if reset = '1' then 
      a <= '0' ;
      fsm_state <= idle ;
   elsif rising_edge ( clock_100mhz ) then	
      case fsm_state is 
         when idle =>	
            if shoot = '1' then
               a <= '1' ;
               fsm_state <= shooting ;
            end if ;					
         when shooting =>
            a <= '0' ;
            fsm_state <= idle ;		
       end case ;
   end if ;
end process ;

As ads-ee mentioned - this is no software!
This code describes a "block of hardware". The syntheses tries to build a logic circuit out of it using whatever FPGA resources it has (i.e - flip flops , muxes , decoders etc...).

ads-ee · May 27, 2015

p11,

I think your problems with understanding VHDL stems more from a lack of digital design basics.

What you've been proposing for your process:

Code:

process
a <= '1';
wait for 10 ns;
a <= '0';
end process;

would have to have a truth table that synthesizes to the following:

Code:

 a | a+
---+---
 x | 0

basically ground a.

a time delay cannot be synthesized, time is not translatable into hardware.

A process without a sensitivity list is synthesizable, only because synthesis doesn't use the sensitivity list (the sensitivity list is required by simulation tools), but the logic that can be synthesized must conform to a certain "template" to be interpreted by the synthesis tool as a specific type of logic (e.g. Flip-Flop, mux, decoder, etc).

To "time" events in hardware you must use a clock and that clock plus a sequencer (e.g. counters, FSM, etc) are what decides when signals transition. See post #25 or #26 for examples of FSMs to time the output events you would want. Once again if you don't want to use a clock and are trying to do this with combinational logic you will fail. It is not possible to create a design in an FPGA that times things without a clock of some sort being used.

I really don't understand your instance on using a process without a sensitivity list and why you are blindly ignoring the recommendations of probably close to 100+ years of experience between the posters that have replied to your thread. I've been writing HDL code for approximately 20 years and I'm pretty sure most of the other posters have as much if not more experience. If you won't listen to our combined 100+ years of coding experience then there isn't much else we can do to help you.

I for one will wait to see if you embrace any of our recommendations before replying further. I feel my time is better spent on posters that are willing to listen to our replies.

Regards

shaiko · May 27, 2015

ads-ee,

Hats off to your patience!
I think the OP has gone into a "thought lock".
He isn't "ignoring" what's written here on purpose. He's just having trouble to grasp the idea behind HDL and the difference between synthesizable and un-synthesizable logic.

p11,
I advice you to do the following thing.
Instead of trying to understand pre written VHDL code - go the opposite way. Draw an arbitrary schematic circuit consisting digital logic primitive (Mux , Flip Flops , AND gates, NOR gates). Connect these in any way you like - don't put any thought behind it.

Post your drawing and we'll help you write VHDL code that DESCRIBES your circuit.

p11 · May 29, 2015

here the inputs are a, b and final output is c . the last gate is a nand gate .

TrickyDicky · May 29, 2015

Its a simple enough problem - doesnt need a process at all..

shaiko · May 29, 2015

Its a simple enough problem - doesnt need a process at all..

That's true,
But just for the sake of it lets write it in a process:

Code:

process ( A , B , C ) is
begin
C <= 
not 
( 
	( not ( A and B ) ) 
	and 
	( not ( ( not ( A and B ) ) or B ) )
) ;
end process ;

-- Given pure combinatorial logic ( no flip flops ) - notice that all signals ( a,b,c ) are in the sensitivity list.

Tetik · May 29, 2015

Just a note, draw the thruth table of your circuit and you will find out that C is always '1'

shaiko · May 29, 2015

Taking it a step further, suppose the output C is connected to the input of a D flip flop. And the output of the flip flop is called: 'Y'.

The new code will look like this:

Code:

process ( clock ) is
begin
  if rising_edge ( clock ) the
    Y <= C ;
  end if ;
end process ;

-- This Flip Flop is sensitive only to the 'clock' signal - so only this signal is in the sensitivity list.

The compiler will "read" our code and interpret it as a simple D Flip - Flop. Because a D-Flip Flop behaves just like that.

This is how HDL works - you "tell the compiler a story" about an animal that walks on 4 , roars and has sharp teeth - the compiler says: that's probably a Lion...

Now, keep in mind that there're VERY strict rules of how to tell an HDL story so that the a compiler will understand you and be able to correlate it to synthesizable logic ("real animals that exists in nature" - not unicorns!).
Using statements such as: "wait for 10ns" is against these rules.

vGoodtimes · May 30, 2015

shaiko said:
Given pure combinatorial logic ( no flip flops ) - notice that all signals ( a,b,c ) are in the sensitivity list.

You shouldn't have 'C' in the list. It may not matter (eg, if the simulator determines 'C' has no effect on the process), but it isn't an input. A change in 'C' will never cause the outputs of the process to change. Placing 'C' into the sensitivity list tells the simulator to do the process a second time if 'C' changes.

shaiko · May 30, 2015

You shouldn't have 'C' in the list. It may not matter (eg, if the simulator determines 'C' has no effect on the process).

You're right - putting C in the sensitivity list isn't a must.
But when I write a complex combinatorial process I want to relieve myself from thinking about "cause and result". Putting all participating signals in the sensitivity list takes care of that for me.

p11 · Jun 2, 2015

shaiko said:
Think of a VHDL process as a block of code that obeys certain rules.
The statements, which describe the behavior in a process, are executed sequentially, in the order you specified them.
Once the last line is exited the values get updated. This repeats itself in an infinite loop.

The "sensitivity list" has no effect on the synthesized logic - it's used for simulation only.
Every time a signal in the sensitivity list is changes - the process is entered. Think of it as a "hint" to the simulator that tells it when to look evaluate the statements inside the process.

OK, THAT MEANS WHEN AM TRYING TO SYNTHESIZE THE code , then no matter watever may be the sensitivity list , the process goes on repeating even if there occurs no change in the signal value of the sensitivity list.

Dan Mills · Jun 2, 2015

You are thinking software again, worse you are thinking sequential execution.

Repeating, well no, because it all happens in parallel, there is no loop.

VHDL in this matter is more like a declarative language, in the first example, you don't actually need a process block, just writing the following in the implementation will do the job

Code:

C <= 
not 
( 
	( not ( A and B ) ) 
	and 
	( not ( ( not ( A and B ) ) or B ) )
) ;

because the logic is not clocked, it the compiler takes that expression and converts it to a little lookup table that takes two electrical inputs and produces one electrical output (Actually it probably notices that the logic simplifies to C <= '1'; but that is a detail).

You are describing combinations of wires, small lookup tables and flipflops, not software.

If you instantiate that block and hook it to some IO pins with switches and an LED you will see the behavior described, there is a propagation delay of course, but timing constraint files are an advanced topic, just know that it is of the order of a few ns.

A process block is mostly useful when describing clocked logic (And in simulation where different rules apply), that is logic that involves flipflops either implicitly or explicitly and it is here that the 'sequential in zero time, with assignments at the end' thing becomes important.

Seriously, this is NOT C, JAVA, PYTHON, you are telling the chip what to BE not what to DO, and the difference is everything.

Get a dev board and play with it, this is the only way to really make this sink in.

(I still have real problems with Verilog in this respect, too much like C for my subconscious, and I have done a lot of C over the years).

Regards, Dan.

Tetik · Jun 2, 2015

It seems that you don't know what are inside a FPGA. It has basically Flip-Flop, LUT, BRAM and PLL. There's no CPU that can execute code. VHDL is a "tool" that describes the hardware that needs to be used. In example, the following code will use a Flip-Flop in the FPGA

Code:

process(clk)
begin
  if rising_edge(clk) then
    Q <= D;
  end if;
end process;

D can be an input pin of the FPGA
Q can be an output pin of the FPGA

It is a very simple example but you need to understand that.

vGoodtimes · Jun 3, 2015

p11 said:
OK, THAT MEANS WHEN AM TRYING TO SYNTHESIZE THE code , then no matter watever may be the sensitivity list , the process goes on repeating even if there occurs no change in the signal value of the sensitivity list.

The synthesis tool only allows process styles that it can synthesize. After synthesis, the result is some form of netlist and the concept of a "process" no longer exists. After further implementation steps the netlist is converted into an actual implementation and the concept of a process certainly only makes sense if the process could have described that implementation.

edit -- Additionally, VHDL/Verilog allow more descriptive, but non-synthesizable, constructs for simulation. VHDL started as a simulation language and later vendors added synthesis support to parts of the language. This has been improving over time, but even now there are theoretically synthesizable constructs that are not supported by all synthesis tools. (Xilinx's Vivado actually didn't recognize VHDL's "group" keyword for several versions. I found this when trying to apply a handful of attributes to a group of signals.)

process statement in vhdl confusion

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