procedure of PROCESS in VHDL

wtr · Jul 27, 2018

Since I have access to the vhdl2008 standard I'd like to give you guys some snippets.

Excerpt from 2008 standard

Section 10 - Sequential statements.
The various forms of sequential statements are described in this clause. Sequential statements are used to
define algorithms for the execution of a subprogram or process; they execute in the order in which they
appear.
sequence_of_statements ::=
{ sequential_statement }
sequential_statement ::=
wait_statement
| assertion_statement
| report_statement
| signal_assignment_statement
| variable_assignment_statement
| procedure_call_statement
| if_statement
| case_statement
| loop_statement
| next_statement
| exit_statement
| return_statement
| null_statement
All sequential statements may be labeled. Such labels are implicitly declared at the beginning of the
declarative part of the innermost enclosing process statement or subprogram body.

11.3 Process statement
A process statement defines an independent sequential process representing the behavior of some portion of
the design.

So we know that a process is sequential, which means all the events ripple one after each other. Then how is it not the case that a=b=c ??

To understand that, one needs to understand VHDLs concept of drivers & transactions & delta cycles.

10.5.2.2 Executing a simple assignment statement
The effect of execution of a simple waveform assignment statement is defined in terms of its effect upon the
projected output waveforms (see 14.7.2) representing the current and future values of drivers of signals.

14.7.2 Drivers
Every signal assignment statement in a process statement defines a set of drivers for certain scalar signals.
There is a single driver for a given scalar signal S in a process statement, provided that there is at least one
signal assignment statement in that process statement and that the longest static prefix of the target signal of
that signal assignment statement denotes S or denotes a composite signal of which S is a subelement. Each
such signal assignment statement is said to be associated with that driver. Execution of a signal assignment
statement affects only the associated driver(s).
A driver for a scalar signal is represented by a projected output waveform. A projected output waveform
consists of a sequence of one or more transactions, where each transaction is a pair consisting of a value
component and a time component. For a given transaction, the value component represents a value that the
driver of the signal is to assume at some point in time, and the time component specifies which point in time.
These transactions are ordered with respect to their time components.
A driver always contains at least one transaction. The initial contents of a driver associated with a given
signal are defined by the default value associated with the signal (see 6.4.2.3). The kernel process contains a
variable representing the current value of the driver. The initial value of the variable is the value component
of the initial transaction of the driver.
For any driver, if, as the result of the advance of time, the current time becomes equal to the time component
of the second transaction of the driver, the first transaction is deleted from the projected output waveform,
and what was the second transaction becomes the first transaction. Then, or if a force or deposit is scheduled
for the driver, the variable containing the current value of the driver is updated as follows:

What is happening in

Code VHDL - [expand]
1
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Process (clock)
begin
if rising_edge (clock) then
b <= a;
c <= b;
end if;
end process;

So going with what the standard tells us.
a is assigned to b at the end of the delta or process here
There is transaction_value = 1, transaction_time = end of clock
b is assigned to c at the end of the delta or process here
There is transaction_value = 2, transaction_time = end of clock/process.
Cometh the end of the process, then these drivers are assigned.

In non-synthesis code you can use after, which changes the transaction_time from next delta.

TrickyDicky · Jul 27, 2018

wesleytaylor said:
So going with what the standard tells us.
a is assigned to b at the end of the delta or process here
There is transaction_value = 1, transaction_time = end of clock
b is assigned to c at the end of the delta or process here
There is transaction_value = 2, transaction_time = end of clock/process.
Cometh the end of the process, then these drivers are assigned..

This could be a little misleading, as you inply that the transaction on c occurs at a different time to b, which is untrue. b and c are assigned in the same delta. So the transaction_time will be current_time + interation_number (all simulators set an interation limit - which is the max number of deltas at current_time). The assignment will be seen on the waveform in the delta cycle after the clock has transitioned to '1'.

ThisIsNotSam · Jul 27, 2018

You guys are confusing the way the simulator interprets the statements (sequential) vs the generated hardware (also sequential). For beginners it is probably not helpful to go into details about how the simulator interprets things, delta cycles, etc. Jut don't go there.

The explanation about the back to back connected flops is the easiest to follow.

procedure of PROCESS in VHDL

wtr

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TrickyDicky

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ThisIsNotSam

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Code VHDL - [expand]
1 2 3 4 5 6 7	Process (clock) begin if rising_edge (clock) then b <= a; c <= b; end if; end process;

procedure of PROCESS in VHDL

wtr

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TrickyDicky

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ThisIsNotSam

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