procedural block instantiation from with in if-else or case statement

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Muddussir

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dear all
is there any way to instantiate procedural block using case/ if-else statement? if not is there any alternative? i am using verilog on xilinx platform for code. for example :

if
synthesize this procedural block
else
synthesize this procedural block

etc.

or a more clear picture is:

if
instantiate procedural block B1
else
instantiate procedural block B2


Please do give me a solution. I am stuck at this step.
 
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Similar problem as in your previous thread https://www.edaboard.com/showthread.php?t=358094

It's only possible as generate for constant parameters. Verilog is hardware description language. A hardware block can't be put in and removed from your logic depending on a variable condition.

It's possible however that the elaboration of the logic is enabled and disabled conditionally. If you want to copy the output of multiple logic blocks conditionally to a variable, a multiplexer might be required.
 
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    Muddussir

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thank you for the explanation. I was thinking on the point that there must be solution to such situations where for an input bit 0 instantiation of B1 and for input bit 1 instantiation of B2 take place. such kind of scenarios are very common. how can we deal these in verilog.
 

It depends. If B1 and B2 are stateless, it's sufficient to multiplex their output. Otherwise it might be necessary to have enable signals and deactivate the unused module.
 
The main options are:
1.) use if-generate to select a module at time of synthesis. The other module is not included in the design.
2.) instantiate both modules, use some logic on the input/output to deal with the selection process.
3.) create a module that can perform both functions. This takes more effort to design and test. This only works if the modules are similar.

There are also methods based on building multiple FPGA configurations or using partial reconfiguration. These involve reprogramming the fpga, or part of the fpga. Partial reconfiguration makes it more difficult to design the project overall.
 

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