Procedural Assignment error (verilog )

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No error is a good start. Now for bonus points use verilog 2001 port syntax.

Code indentation is still messed up.

Keep improving on those skills, or you might as well go straight to middle management.
 

You might have no errors, but you certainly must have warnings.

You have instantiated core_v 3 times in register2, and your instantiations have 5 ports, but core_v only has 4 ports. Plus, your instantiations use signals that do not even exist in register2 (i.e. s0, si, s2, q0,q1).

You don't seem to use the module registerr1 for anything.

All your always blocks will create latches rather than flip flops.

What hardware do you think this code will make?

r.b.
 

No error, yeah right....

Code: 
xvlog crap.v
INFO: [VRFC 10-165] Analyzing Verilog file "crp_code.v" into library work
INFO: [VRFC 10-311] analyzing module core_v
INFO: [VRFC 10-311] analyzing module registerr1
INFO: [VRFC 10-311] analyzing module register2

xelab -debug typical -timescale 1ps/1ps register2
Vivado Simulator 2014.2
Copyright 1986-1999, 2001-2014 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2014.2/bin/unwrapped/win64.o/xelab.exe -debug typical -timescale 1ps/1ps register2
Multi-threading is on. Using 6 slave threads.
Starting static elaboration
ERROR: [VRFC 10-29] core_v expects 4 arguments [crp_code.v:36]
ERROR: [VRFC 10-29] core_v expects 4 arguments [crp_code.v:38]
WARNING: [VRFC 10-278] actual bit length 4 differs from formal bit length 1 for port clk [crp_code.v:37]
WARNING: [VRFC 10-278] actual bit length 4 differs from formal bit length 1 for port clk [crp_code.v:38]
WARNING: [VRFC 10-278] actual bit length 4 differs from formal bit length 1 for port clk [crp_code.v:36]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.

You have a module core_v with 4 ports and an are trying to instantiate a 5 port module.

See my comment in #13 about using named port connections. Also use Verilog 2001 module port declarations...it will make you appear less like an Verilog HDL Neanderthal. Seriously it's 2014 and your using syntax from 1987, even if you look at it as 1995 (year it was made an IEEE standard) syntax then your still using 19 year old syntax, when the newer (2001) syntax is supported by pretty much any tool you'll ever use.

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mrflibble said:
Keep improving on those skills, or you might as well go straight to middle management.
Click to expand...
I already suggested they should skip the development of technical skills and just go for management (business) directly ;-). Though let us know where you end up so I can avoid working for you.

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rberek said:
Plus, your instantiations use signals that do not even exist in register2 (i.e. s0, si, s2, q0,q1).
Click to expand...
Actually there's nothing wrong with doing this (as it's positional) except for the fact that it's very confusing and you'll likely hook something up wrong.

Regards
 

ads-ee said:
Actually there's nothing wrong with doing this (as it's positional) except for the fact that it's very confusing and you'll likely hook something up wrong.
Click to expand...

Which is another way of saying: "while the code may be syntactically and even functionally correct, it will result in your project soon becoming an unmaintainable steaming pile".
 

now I think It should be correct with no error
Code: 
module core_v(clk, ld, d0, q0,d1,q1,d2,q2);
        input  [3:0] d0,d1,d2;
        input clk;
        input ld;
        output [3:0] q0,q1,q2;
        reg [3:0]q0,q1,q2;
        always @(posedge clk)
        begin
           if (ld==1) q0 <= d0;
           end
        always @(posedge clk)   
           begin
           if (ld==1) q1 <= d1;
           end
        always @(posedge clk)
        begin
           if (ld==1) q2 <= d2;
           end
endmodule
 

Should work, could still use some comments, better formatting, and Verilog 2001 port declarations (but I'll assume your professor is a HDL Neanderthal and wants you to use prehistoric Verilog 87 syntax ;-))
 

look at post #5 there is link then see figure 2.10
i want to add alu ,accumulator

give idea I can made without instantiating module or I need instantiating module

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look at post #5 there is link then see figure 2.10
I wrote code for that circuit
I know this code look messy I will write code in good formmet but look this code
i compiled with no error
Code: 
module core_v(clk, ld, d0, q0,d1,q1,d2,q2,d3,q3, z,a,b,sel);
        input  [3:0] d0,d1,d2,d3;  // input for r0, r1 ,r2 acc
        input clk;
        input ld;
        output [3:0] q0,q1,q2,q3;  // output for r0,r1 ,r2 acc
        reg [3:0]q0,q1,q2,q3;
        always @(posedge  clk )
        begin
           if (ld==1)
           begin
                q0 <= d0;       /// output r0
                q2 <= d2;        // output r1
                q1 <= d1;        // output r2
                q3 <= d3;        // output acc
           end
       end
        
     
input [8:0]a,b;      // input for alu 
input [3:0]sel;
output [8:0]z;       // output for alu 
reg [8:0]z;
always@(sel,a,b)
begin
case(sel)
4'b0000: z=a+b;
4'b0001: z=a-b;
4'b0010: z=b-1;
4'b0011: z=a*b;
4'b0100: z=a&&b;
4'b0101: z=a||b;
4'b0110: z=!a;
4'b0111: z=~a;
4'b1000: z=a&b;
4'b1001: z=a|b;
4'b1010: z=a^b;
4'b1011: z=a<<1;
4'b1100: z=a>>1;
4'b1101: z=a+1;
4'b1110: z=a-1;
endcase
end
endmodule
 

I know this code look messy I will write code in good formmet but look this code
Click to expand...
Since you already know your code looks messy, I will read it when you've cleaned it up then. No rush.

Incidentally, try using:

Code Verilog - [expand]
1

// my pretty code


Code Verilog - [expand]
1
2
3
4

module core_v (
    input clk,
    input sel,
    // etc


In the end it's even less work for you, because sometimes when you make a mistake copy/pasting code to forum, the syntax highlighting helps in spotting it.
 

I know this code look messy I will write code in good formmet but look this code
i compiled with no error
Click to expand...
Ummm, this line won't compile:
4'b0100: z=a&&b;

Now disregarding the typo yes it will compile, but I would advise against burying input and output declarations deep in the middle of your code. That's why I keep telling you to use Verilog 2001 port declarations (keeps one from have such bad habits).

Errors like this are the reason you should format code so it's readable. You might notice mistakes like this if you CAN READ IT.
Imsureyoucanreadthisjustfinebecauseitsformatedjustlikeyourcode.
White space is your friend use it.

Who indents 8 spaces!? Your indenting is haphazard to say the least, set your text editor to indent something like 2, 3, or 4 spaces and stick with it. It also doesn't hurt (or take any time) to type the [ENTER] key once in a while to add some white space between lines.

Looking at all the code you've posted makes me feel like all I've been doing is banging my head against the wall, while you have been playing loud music through noise reduction headphones, so you can ignore the banging sounds. Really if you don't want my help then tell me to leave you alone.

Regards
 

And that is why I won't even read it before he cleans it up. Replying to poorly readable code just enables bad habits. Someone else is free to do so, but I am not going to waste time on it.

So there you have it. Want help? Clean it up.

- verilog-2001 port syntax
- proper indentation (4 spaces should do the trick. no tabs.)
- syntax=verilog tag

Chop chop, get to it. Not that hard. It's good for you. You know you want to. It will make you a better person. Before you know it, it will rain cute kittens.
 

Since you already know your code looks messy, I will read it when you've cleaned it up then.
Click to expand...
ok look here
Code: 
//component 
//register r0
//register r1
//register r3
//accumulator 
//alu
//connect all component in module 

module core_v (clk, ld, d0, q0,d1,q1,d2,q2,d3,q3, z,a,b,sel);
        //Input Port Declarations
        input  [3:0] d0,d1,d2,d3;   // input data for r0, r1 ,r2 acc
        input  clk;                 // clock signal 
        input  ld;                  // load signal
        input  [8:0]a,b;            // input for alu 
        input  [3:0]sel;            // select input 
        output [8:0]z;
        output [3:0] q0,q1,q2,q3;   // output for r0,r1 ,r2 acc
        reg    [3:0] q0,q1,q2,q3;
        reg    [8:0]z;              //
        always @(posedge  clk )     //
        begin                       // start 
           if (ld==1)
           begin
                q0 <= d0;       /// output r0
                q2 <= d2;        // output r1
                q1 <= d1;        // output r2
                q3 <= d3;        // output acc
           end
       end                        // end   
   
always@(sel,a,b)
begin
case(sel)
4'b0000: z=a+b;
4'b0001: z=a-b;
4'b0010: z=b-1;
4'b0011: z=a*b;
4'b0100: z=a&&b;
4'b0101: z=a||b;
4'b0110: z=!a;
4'b0111: z=~a;
4'b1000: z=a&b;
4'b1001: z=a|b;
4'b1010: z=a^b;
4'b1011: z=a<<1;
4'b1100: z=a>>1;
4'b1101: z=a+1;
4'b1110: z=a-1;
endcase
end
endmodule

Ummm, this line won't compile:
4'b0100: z=a&&b;
Click to expand...
I compiled with no error
you don't want my help then tell me to leave you alone.
Click to expand...
I have downloade pdf file for 2001 port syntex
I don't want to hurt you I always respect all member they always help lot of stupid student like me
 

vead said:
ok look here
Click to expand...
I looked. Same shit.

Try this first:
- verilog-2001 port syntax
- proper indentation (4 spaces should do the trick. no tabs.)
- syntax=verilog tag

I have downloade pdf file for 2001 port syntex
Click to expand...
Good to know. Progress! Now read it, and actually use that verilog 2001 port syntax in your code.
 

vead said:
I don't want to hurt you I always respect all member they always help lot of stupid student like me
Click to expand...
Well you're giving me a headache.

Actually by not modifying the code and using the syntax tags you are exhibiting a lack of respect to the forum members trying to help you. The requests that have been made to improve the readability of the code are not difficult or all that time consuming. You only need to do this once and each time you add new code. On the other hand by not reformatting your code you are saying "I don't care that you have to repeatedly copy the code into a text file and waste time reformatting the code every time I post more unformatted garbage".

Formatting is important, it shows an organized mind. It also shows your respect for others by making it easy to read your code. Adding good comments is also helpful for others to interpret what the intent of the code was, so get in the habit of adding comments as you write your code.

Regards
 
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