Problems with simulating hierarchical design in Cadence

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Vonn

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c@dence

Hi every body, Iam trying to simulate my verilog code using c@adence tools .. when I tried to use Veril0g-XL .. it works well for a single module but I faced a problem with my Hierarchical Design ..the tool can't see the nested components and there is an error (module or primitive not defined verilog-MPND) ... ok how to define them ? I put all my files in the same directory as I used to do with X!l!n!x ... my code is working with X!l!n!x but because Iam new to c@adence I just don't know how to make the tool to see the other components in the Hierarchical Design ?
any body can give me a hand ... thanx
 

Re: c@dence

You can edit a filelist file.
for example:
### filelist
./top.v
./**.v
./**.v
### endof filelist

then you can use

ncverilog -f filelist

that 's ok!!
 

c(at)dence

1) you may wdit a batch file suchas: run
" verilog -v yourcodelist +gui - "

verilog admit you to write the *.v in your run direction.
 

Re: c@dence

well some friend told me very easy way to do it and I would like to share it with you because I found many questions - like mine - on the internet without answer
so the answer will be :
from virtu0s0 ver!log environment for ver!log-XL integrator window:
1- click setup
2- click simulate
3- click more
4- link all your ver!log files in the library files field (with path)

hope that help others also
thanx
 

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