Problems with interfacing JOP and Wishbone

Java Optimised Processor

Hi,
I am doing a project which includes interfacing JOP with I2s via Wishbone.input and output of wishbone is parallel(32 bits).
In JOP the output comes in two ways
1.via UART.(serial output)
2.via external memory.(parallel output)
so i am opting the second one to connect it to wishbone.
now the problem is i downloaded whole code of JOP from opencoes.org,and checked on xilinx kit.(VHDL code).
I wrote an interface code to interface wishbone and jop.I am unable to instantiate the component from JOP which produce the parallel output to the interface code. Its showing errors.can anyone who have knowledge on JOP please explain me what to do.
i could'nt figure out what rama_ncs,rama_nlb,rama_nub,ramb_ncs,ramb_nlb,ramb_nub.ram_noe,ram_nwe..and how to connect this to the interface..
eagerly waiting for solution.
Tan

Re: Java Optimised Processor

The most recent version of JOP is at h**p://www.jopdesign.com and not opencores.

the_penetrator©

Re: Java Optimised Processor

Hello,
I even went through that site.please clear my doubt regarding the code.

Added after 3 hours 40 minutes:

Hi friends,
I want to connect Jop to wishbone.This can be done by designing a block which connects jop and wishbone.But the output of jop is having an address bus of 18 bits and wishbone input address bus is of 8bit.And as i mentioned in the above post i am unable to get information about the above signals.Any suggestion is appriciated.
waiting for the solution
cheers
Tan.