Problems with Altera 20K200E FPGA pins

[kingkang]

Altera FPGA pins problem

Hi
I synthesised my verilog code in synplify.
And do the P&R in quartusII.
When I did not config some of the pins FPGA
ran correctly.But when I config these pins,it
went wrong result! I can believe the pins did not
affect the internal function!
The board freq meet the timing report of quartusII.
I don't know why.
The fpga is Altera 20k200e

Thanks and Regards

 

[davorin]

Re: Altera FPGA pins problem

What pins did you configure and what exactly?
Error output?

 

[ifarmer]

@ltera FPGA pins problem

I guess that is because your pin assignments are not suitable with your design and device. Some device limitation, such as clock pin location, oe group limitation, leads Quartus failed P&R your design.