Problems with a PLL: Transistor Sizing (VCO related)

PLL: Transistor Sizing ?

Hi members,
I designed a PLL in order to use its output as a clock signal for other digital components designed at the transistor level.
I was surprised when I gathered the hole parts. The PLL frequency decreased to the half of it's value ????

The simulation of the PLL alone was Ok, I didn't get what happen now.

I thought that this may be due to the additional load capacitance introduced when connecting the pll to the other parts.
I thought also that the problem is due to the VCO and the solution is to enhence it to deliver a higher current and that is possible by widening the transistors used to construct the VCO.
Are my thougths right ?

Please help.

Re: PLL: Transistor Sizing ?

hello,
i think you're right, i faced the same problem with an ldo, the simulation of the device alone was great, but once i simulate it with all the other blocs it was a disaster.

PLL: Transistor Sizing ?

So what did you to solve the problem ?

Re: PLL: Transistor Sizing ?

You have to foresee and design a buffering into the VCO. Otherwise the VCO frequency gets modulated by load changes.

Re: PLL: Transistor Sizing ?

rfsystem said:

You have to foresee and design a buffering into the VCO.

Click to expand...

Do you mean introduce buffers between Delay cells ?

Otherwise the VCO frequency gets modulated by load changes.

Click to expand...

Could you please explain ?

Thanks

Re: PLL: Transistor Sizing ?

You have to foresee and design a buffering into the VCO

Click to expand...

I inserted a Buffer at the output of the PLL (so the VCO) and the frequency decreased.

My question are:
1-

Do you mean introduce buffers between Delay cells ?

Click to expand...

2- Now, If I Introduce buffers between Delay cell, VCO frequency will decrease or will not be affected ?
3- Do you mean that this solution is better than the transistor sizing solutions ? Or you don't see that the last don't resolve the problem.

Thanks in advance my friend.

Re: PLL: Transistor Sizing ?

No, not in between the delay cells but parallel depending on the number of phase you use. Typical use minimum inverter and boost then. The delay cells have to scale a little above minimum inverter so that th additional delay is low.

If you simulate the VCO including buffer with different load cap at the buffer the VCO frequency will change. But after two inverters the change is small.

Re: PLL: Transistor Sizing ?

The VCO is a differential and has 4 delay cells:

No, not in between the delay cells but parallel depending on the number of phase you use.

Click to expand...

Sorry I didn't get what do you mean by parallel.

PLL: Transistor Sizing ?

for each delay cell in ur vco, there should be a buffer with it.
say A is ur delay cell, B is the buffer, ur vco should be like
A1 drives A2 and B1, A2 drives A3 and B2, and so on.

and make sure each delay cell has the same loading.