Problems with 8 bit DDS as it stops "half way"

echo47 said:

What is the name of the software that's showing you the incorrect waveform?

Can you show us a screen image of the malfunction you see?
Have you configured your waveform viewer to show signed (positive and negative) values?

In your VHDL testbench, where is your "DDS" component? If it's a core, which one did you use, and what parameters did you specify to create it?

Your testbench simulates fine in ModelSim 6.3c. I generated an 8-bit DDS core using Xilinx coregen and "DDS Compiler 2.0". The clock is 500 MHz, the sinewave is 120 MHz. Here's a screen image. The vertical scale on the "sine" signal is from -128 to +127:

Click to expand...